VHDL Code for 4x4 Mult: SYNTAX OK BUT ERROR:HDLCompiler:1029

Question

Hello this is my first post here, I have some code that I've written that I'm having trouble with. I was hoping I can get some help.

I'm having some issues with my VHDL code for a 4x4 multiplier.

The schematic I'm using is below: 4x4 Multiplier

Running a Syntax check goes through just fine but I get the following error:

ERROR:HDLCompiler:1029 - "T:/Multiplier/mult.vhd" Line 26: No index value can belong to null index range
ERROR:Simulator:777 - Static elaboration of top level VHDL design unit mult in library work failed

I was able to find something similar to the first Error: https://forums.xilinx.com/t5/Simulation-and-Verification/HDLCompiler-error-1029-in-a-XilinxCoreLib-VHDL-file/td-p/153914

and he was able to fix his error by changing the size of his std_logic_vector

But I've used up all of my vector assignments and all of my signals are defined for my sumouts and carrys. The half adder and full adder source codes attached to the project were tested and working.

Any idea? The code is below. Please and thank you! I'm new here, though I've one my research and came up unsuccessful.

--4x4 Multiplier
library ieee;
use ieee.std_logic_1164.all;
entity mult is
port (x,y:IN std_logic_vector (3 downto 0);
 p:OUT std_logic_vector (7 downto 0));
end mult;
architecture mult_beh of mult is
component ha 
 port(a,b: IN std_logic;
 c,s: OUT std_logic);
end component;
component fa 
 port(a,b,cin: IN std_logic;
 cout,sum: OUT std_logic);
end component;
signal andgate: std_logic_vector(15 downto 0);
signal sumout: std_logic_vector(11 downto 0);
signal carry: std_logic_vector(11 downto 0);
begin 
 andgate(0) <= x(0) and y(0);
 andgate(1) <= x(1) and y(0);
 andgate(2) <= x(2) and y(0);
 andgate(3) <= x(3) and y(0);
 andgate(4) <= x(0) and y(1);
 andgate(5) <= x(1) and y(1);
 andgate(6) <= x(2) and y(1);
 andgate(7) <= x(3) and y(1);
 andgate(8) <= x(0) and y(2);
 andgate(9) <= x(1) and y(2);
 andgate(10) <= x(2) and y(2);
 andgate(11) <= x(3) and y(2);
 andgate(12) <= x(0) and y(3);
 andgate(13) <= x(1) and y(3);
 andgate(14) <= x(2) and y(3);
 andgate(15) <= x(3) and y(3);
 --Gates
 ha0: ha port map(s => sumout(0), a => andgate(1), b => andgate(4), c => carry(0));
 fa0: fa port map(sum => sumout(1), a => andgate(2), b => andgate(5), cout => carry(1), cin => carry(0));
 fa1: fa port map(sum => sumout(2), a => andgate(3), b => andgate(6), cout => carry(2), cin => carry(1));
 ha1: ha port map(s => sumout(3), a => carry(2), b => andgate(7), c => carry(3));
 ha2: ha port map(s =>sumout(4), a => sumout(1), b => andgate(8), c => carry(4));
 fa2: fa port map(sum => sumout(5), a => sumout(2), b => andgate(9), cout => carry(5), cin => carry(4));
 fa3: fa port map(sum => sumout(6), a => sumout(3), b => andgate(10), cout => carry(6), cin => carry(5));
 fa4: fa port map(sum => sumout(7), a => carry(3), b => andgate(11), cout => carry(7), cin => carry(6));
 ha3: ha port map(s => sumout(8), a => sumout(5), b => andgate(12), c => carry(8));
 fa5: fa port map(sum => sumout(9), a => sumout(6), b => andgate(13), cout => carry(9), cin => carry(8));
 fa6: fa port map(sum => sumout(10), a => sumout(7), b => andgate(14), cout => carry(10), cin => carry(9));
 fa7: fa port map(sum => sumout(11), a => carry(7), b => andgate(15), cout => carry(11), cin => carry(10));
 --Assigning p values
 p(0) <= andgate(0);
 p(1) <= sumout(0);
 p(2) <= sumout(4);
 p(3) <= sumout(8);
 p(4) <= sumout(9);
 p(5) <= sumout(10);
 p(6) <= sumout(11);
 p(7) <= carry(11);
end mult_beh;

Answer 1

You defined all your vector ranges in the wrong direction. If you want to use downto then the left index must be greater than the right index, e.g.:

signal andgate: std_logic_vector(15 downto 0);

Or change the direction to to in your code to number the bits in ascending order.