Cannot Find the Syntax Error Near Process

Question

I'm very new to VHDL and this one must be a really easy question. The code gives me the error that there is a syntax error near the last process, please take a look:

library IEEE; use IEEE.STD_LOGIC_1164.ALL;

entity fsm is
 Port ( D : in STD_LOGIC_vector(1 downto 0); 
 CLK : in STD_LOGIC;
 outLed : out STD_LOGIC);
end fsm;
architecture Behavioral of fsm is
 type state_type is (s1,s2,s3,s4);
 signal next_state, state: state_type;
begin
 process(CLK)
 begin
 if rising_edge(CLK) then
 state <= next_state;
 end if;
 end process;
 outLed <= '1' when state = S1 and D = "01" else
 '1' when state = S2 and (D = "01" or D = "10") else
 '1' when state = S3 and (D="01" or D= "10") else
 '1' when state = S4 and D="10" else
 '0';
 process(state, clk) begin
 case state is
 when S1 =>
 if D= "01" then next_state <= S2;
 else next_state <= S1; end if;
 when S2 =>
 if D="10" then next_state <= S1;
 elsif D = "01" then next_state <= S3;
 else next_state <= S2; end if;
 when S3 =>
 if D = "10" then next_state <= S2;
 elsif D = "01" then next_state <= S4;
 else next_state <= S3; end if;
 when S4 =>
 if D = "10" then next_state <= S3;
 else next_State <= S4; end if;
 when others =>
 next_state <= S1;
 end process;
end Behavioral;

Thank you.

• user16324: the process ends before the end of the case statement end case; Admittedly the compiler could give a clearer error message; others usually do.

Answer 1

There needs to be an "end case" statement, before the "end process" statement. This is basic vhdl syntax. Despite writing a lot of VHDL over the years, I didn't know by looking at it. I just googled it.