False rail to rail buffer?

Question

My question, as the title suggests, is about a simple opamp that looks like it exhibits rail to rail DC characteristic when used as a buffer. The opamp per se is a simple 2-stage PMOS input stage with a second stage that is an nmos common source amplifier with the Miller capacitor and Resistor for compensation. Positive supply of 1.8 V and VSS = 0V, load = 0.1 pF.

When this opamp is connected as a unity gain buffer and its DC characteristic plotted, by stepping the input from ground to VDD, I noticed that the output follows the input perfectly for Vin > 200 mV and even extends to VDD! The small limit on the low side is expected but since it is a pmos input stage I also expected the output to saturate much lower than VDD due to input common mode range. This almost seems rail to rail?!

I checked the loop gain for different common mode input values and I indeed noticed, as expected theoretically, that for high DC values the loop gain is low and when approaching VDD there is no gain (<0 dB), this would mean that there is no gain thus the negative feedback should fail.

Am I right to assume that this strange behavior — the 'false' rail to rail — is due to some other phenomenon? All transistors go to triode at high input values (>1.3 V) and some at subthreshold. Have you encountered this before? I am assuming that the when rail-to-rail is used in the literature they mean gm is constant for all valid input ranges, but this DC-characteristic should not be observed in the first place?

I have attached an image of the DC-DC characteristic, this plot is not from cadence (where it was simulated) but it is the exact same characteristic. (I have also attached the opamp schematic for clarity.)

I am mostly looking for a theoretical reply for this phenomenon.

DC characteristic

pmos input opamp

• JYelton: Asking the community not to downvote your question is actually a reason to downvote a question on its own. Your question will get votes (up or down) based on its quality or lack thereof. Further, this is a Q&A, not a forum, so you should not be expecting "a discussion."
• Scott Seidman: Is this a homemade op amp, or is there a part number we can use to pull a data sheet?
• george: @ScottSeidman It is a 'homemade' op amp i.e. simulated in cadence

Answer 1

You do not have a resistive load (just a capacitative one). Therefore, when M5 is completely off, there is no path for DC to flow through M8. Even though M8 is only slightly turned on, with no current through it, there will be no voltage drop across it. Therefore, the output voltage can rise to the positive rail voltage.

However, if you add a resistive load, I strongly believe this "strange behavior" will disappear. The output will no longer be able to reach the positive rail.

• Kuba hasn't forgotten Monica: Yup. CMOS op-amps without a resistive load can look pretty good indeed. Good from afar, but far from good.
• george: Thank you for the answer, much appreciated. Indeed a resistive load of value say 100kohm made the output saturate at a value close to 1.4V.

Answer 2

Consider M8 to be a current source, with compliance voltage limited to the supply, in series with M8's own \$R_{DS(ON)}\$:

schematic

^{simulate this circuit – Schematic created using CircuitLab}

Clearly, with M5 "off" (left), there's nothing preventing the output from rising all the way to \$V_{DD}\$. And with M5 at minimum \$R_{DS(ON)}\$ (right), the only constraint is that very \$R_{DS(ON)}\$, which will develop a voltage very close to zero, but not quite, due to M8's current.

That's pretty much rail-to-rail, by any practically achievable standard, and it has nothing to do with anything else in that design, except perhaps for any constraint the rest of the circuit might impose on M5's \$V_{GS}\$.

• george: I appreciate the insight, thank you for your answer.