Questions tagged [buffer]
A circuit or sub-circuit that as accurately as possible preserves the voltage characteristics of a signal while providing additional current. Typically used in situations where a circuit cannot drive the load that is presented to it.
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False rail to rail buffer?
My question, as the title suggests, is about a simple opamp that looks like it exhibits rail to rail DC characteristic when used as a buffer. The opamp per se is a simple 2-stage PMOS input stage ...
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Can I eliminate the input buffer of this circuit?
I have a circuit made of high-pass and low-pass filters. It currently includes an input buffer, but I’m wondering whether that buffer is necessary. Removing it would let me fit the design into four ...
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Buffer for FTDI to avoid leakage
I am using FT2232HL FTDI device for USB to JTAG purposes. JTAG connects to MCU only, no other devices are on the chain. Since the FTDI PWR is from a USB (using LDO to stabilize it to 3v3), I want to ...
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What is the best way to build a level shifter?
I want to convert 24 V from industrial sensors to 5 V to process it with an Arduino without damaging it. I thought of a voltage divider with a buffer in this constellation:
Is this overkill or is ...
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PCB Technique for unused clock buffer driver outputs
I am using a clock buffer driver in order to create 6 clock signals from one external clock signal.I am using the CY2CC810OXI-1, which provides 10 total outputs, however as said I am only using 6 of ...
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STM32 ADC and Comparator Interference
I have 3 wire, 3-phase system which I am trying to monitor with an STM32G473CET6 which has Differential ADCs and built in comparators.
I am using voltage dividers between the phases to measure L-L ...
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Simplify octal buffer circuit
I'm building an open source device with an audio circuit that connects to a piezo buzzer. While I wait for some components to arrive I'd like to do some tests and finish preparing the PCB design to ...
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Using SN74LVC1G125DBVR as a Line Driver for ICS52000 Microphones
I'm working on a system using a Teensy 4.1 MCU and eight ICS52000 microphones. Each microphone is mounted on its own PCB, and I'm connecting them to the MCU usingn long 50cm FFC cables.
System ...
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Latch bus with FPGA issues
I have an FPGA that send data from a shared bus(the bus called COM(0:15)), which is connected to three buffers. Each buffer is connected to the same bus, and the FPGA controls which buffer will drive ...
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Is a buffering always needed when running signals in parallel for a guitar amplifier effects loop
I'm building an effect looper for my guitar rig, so I can set multiple pedals in or out of the chain with a single switch. I recently got the idea to make the last two loops configurable to either ...
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Can you use RS-422 to transmit a clock
We would like to use RS-422 to send a clk to a remote FPGA on a CCA. I have attached a block diagram of what we would like to do. The FPGA on CCA 1 can use a differential pair, but the buffer ...
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Voltage output with enable?
It's been a long time since I've designed an electronic circuit, can someone please advise the best was to handle this problem.
I have a trigger switch as seen below, the voltage value of SPEED_CTRL ...
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Charge pump with MOS-error-amplifier, please help me understand this circuit
Could you please help me understand how this circuit works?
In my RF classes I was introduced the Charge pump and at some point we were given these two following schematics:
NOTE: I have no idea where ...
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Is parallel buffering with ISR possible?
Speaking generally, given a time-critical module and an MCU (act as buffer),.
If we look at the datasheet of the module, we know the timing diagram. Then, it's possible we can read the module through ...
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Can a system with a clock slower than the signal sample rate reliably process data using buffering without information loss?
I am trying to understand the limitations of signal processing when the system clock is slower than the incoming signal's sample rate and whether buffering can help mitigate this. Specifically, I have ...