While loop in test bench of and gate. getting no output

Question

I have written a simple test bench for and gate. My code and test bench was working fine. Now what I want to do is " I am trying to implement a while loop for my cases". I am not getting syntax error but not seeing any output. can any body tell my mistake?.

timescale 1ns / 100ps

int count=0; module and_gate_test;

// Inputs
reg in1_t;
reg in2_t;
// Outputs
wire out_t;
// Instantiate the Unit Under Test (UUT)
and_gate and_gate_1 (in1_t,in2_t,out_t);
initial 
begin
 // Initialize Inputs
 //case 0
 while(count==100){
 in1_t <= 0;
 in2_t <= 0;
 #1 $display ("out_t=%b",out_t);
 //case 1
 in1_t <= 1;
 in2_t <= 1;
 #1 $display ("out_t=%b",out_t);
 //case2
 in1_t <= 0;
 in2_t <= 1;
 #1 $display ("out_t=%b",out_t);
 //case3
 in1_t <= 1;
 in2_t <= 0;
 #1 $display ("out_t=%b",out_t);
 count++; }
 // Add stimulus here
end

endmodule

Answer 1

Your code never enters the while loop because count is initialized to zero before checking the while==100 condition. Even if the condition wasn't broken, the brace after it would break the rest of the code. I think this is what you're trying for:

// Inputs
reg in1_t;
reg in2_t;
// Outputs
wire out_t;
// test variables
integer count;
// Instantiate the Unit Under Test (UUT)
and_gate and_gate_1 (in1_t,in2_t,out_t);
initial 
 begin
 // Initialize Inputs
 for (count=0; count<=100; count=count+1) begin
 //case 0
 in1_t <= 0;
 in2_t <= 0;
 #1 $display ("out_t=%b",out_t);
 //case 1
 in1_t <= 1;
 in2_t <= 1;
 #1 $display ("out_t=%b",out_t);
 //case2
 in1_t <= 0;
 in2_t <= 1;
 #1 $display ("out_t=%b",out_t);
 //case3
 in1_t <= 1;
 in2_t <= 0;
 #1 $display ("out_t=%b",out_t);
 end
 end

• Pentium100: Is there any reason to use for-case structure?
• travisbartley: No, there's also no reason for the for loop, but it looks like that was what he was trying to do from his question and code. It might be useful if he wants to repeat the tests in some pattern.
• Pentium100: he was trying to use a while loop instead of for that loops the tests 100 times (as I understand it), so far I only saw two mistakes - no "count=0;" before while and "count==100" instead of "count<100" or "count<=100" as the check for the loop.
• travisbartley: OK, I saw the words "case" and thought thats what he wanted a case statement. But you're right, he probably just means it as test case. The {} after the while would also break the code. {} is concatenation in Verilog, not grouping syntax.
• Pentium100: That's why I commented your answer instead of posting my own - I don't really know much about Verilog, the syntax looked similar to C though. So, I guess he made a third mistake, using C style {} instead of begin end.