For-Loop and repeat synthesis

Question

We all know that the For-loop and Repeat are synthesizable, they get converted to blocks, for example:

for (idx = 0; idx < 4; idx=idx+1) begin
a = a + b[idx];
c = c + 2; //You can change more than one variable in a for loop
end

In that example, the resulting hardware will be a chain of adders, summing the values from four array indices.

So my question is what if the For loop iterates over a huge number let's say 10000 ? Will it create a 10000 adders ?!

• Huisman: Please check whether you mean "adders" or "additions" and change your original question if necessary.

Answer 1

Yes, but synthesis tools have a 'maximum loop' value at which they stop.

You can change the value but the default seems to be set rather high.
If you get a warning it is very likely that you have done something wrong.

• DonFusili: +1 Default value for all versions of Vivado, Quartus II, ISE and Synopsis compiler that I've tested is 10000 on clean installs.
• Oldfart: Thank you @DonFusili. I have never tested this so I could not give an actual number.
• Attila Kinali: Side note: While most (all?) FPGA tools will happily synthesize for-loops, ASIC synthesis tools will quite often puke when encountering any kind of loop.
• Greg: @AttilaKinali , I don't know where your getting your info about loop support with ASIC; but it is not true. ASIC synthesizers support for-loops (procedural and generate) and SystemVerilog foreach-loops so long as they can be static unrolled (same for FPGA).
• Attila Kinali: @Greg I had bad experiences with various ASIC synthesizers. FPGA synthesizers seem to be quite a bit more relaxed what they accept and what they can produce proper output for. Though, I have to admit, I have been only using Cadence for the last few years and that does mostly a decent job.