Will temp variable in always_comb create latch

Question

I have following code snippet where a temp variable is used to count number of 1s in an array:

 // count the number 1s in array 
 logic [5:0] count_v; //temp
 always_comb begin
 count_v = arr[0];
 if (valid) begin
 for (int i=1; i<=31; i++) begin
 count_v = arr[i] + count_v;
 end
 end
 final_count = count_v;
 end

Will this logic create a latch for count_v ? Is synthesis tool smart enough to properly synthesize this logic? I am struggling to find any coding recommendation for these kind of scenarios.

Another example:

logic temp; // temp variable
always_comb begin
 temp = 0;
 for (int i=0; i<64; i++) begin
 if (i>=start && i<start+3) begin
 out_data[temp*8 +: 8] = in_data[i*8 +: 8];
 temp = temp + 1'b1;
 end
 end
end

Above example is related to bit slicing where the input is 64Bytes and the output is less than 64Bytes (3Bytes for example, starting from byte# start). I know that there are better ways to code this but I still want to know how the synthesis tool will interpret the design here.

• Matt: I don't know. I'm guessing the second one would be "no", the first case "maybe". Synthesize it yourself and let us know. It should be easy to check.
• The Photon: I don't know enough SystemVerilog to answer this confidently, but think about what count_v represents. You declare it as a single 6-bit signal. But actually in each iteration of the for loop, it represents the output of a different adder. So there are actually 31 different signals that are called count_v in different iterations of the for loop.
• The Photon: Also, the hardware described by the first code will be quite slow because any change in arr[1] has to propagate through 31 adders before final_count will get its correct resulting value.

Answer 1

If within the always_comb block your assignment comes before any read access, there is no latch. You should get an error if there is any possible flow through the block if there was a read before any write to a local variable.