I am trying to understand how the copying of the dynamic arrays work in SystemVerilog. Here is a small code snippet I was trying:
//dynamic_array
module dyn_array();
//2 dynamic arrays of integer type
int dyn1[];
int dyn2[];
initial
begin
//allocate 5 mem location to dyn1
dyn1 = new[5];
//populate the elements of the dyn array
dyn1 = '{1,2,3,4,5};
$display("the value of dynamic array is %p", dyn1);
//copy method
//method1: entire array elements are deleted and copied into new array
dyn2=dyn1; //they point to the same memory
$display("the value of dynamic array dyn2 is %p", dyn2);
//changing value of element in dyn2
dyn2[2] = 10;
//this change will NOT reflected into dyn1. Why?
//Ideally dyn2 should point to the same memory location in dyn1
//why is the change not reflected in dyn1?
//dyn1 = 1,2,3,4,5, dyn2=1,2,10,4,5
$display("dyn1 after change of dyn2 is %p", dyn1);
$display("dyn2 after change of dyn2 is %p", dyn2);
//the previous elements are erased and it will create 10 locations
dyn1 = new[10];
//dyn1 will be empty 10 element array with 0s
$display("dyn1 after new[10] is %p", dyn1);
//dyn2 will be unchanged- 1,2,10,4,5
$display("dyn2 after new[10] is %p", dyn2);
dyn2 =new[10/*new size*/](dyn2); // 1,2,10,4,5,0,0,0,0,0
$display("dyn1 after new[10](dyn2) is %p", dyn1); //dyn1 should be unchanged
$display("dyn2 after new[10](dyn2) is %p", dyn2);
end
endmodule
Here are the simulation outputs on Modelsim:
# the value of dynamic array is '{1, 2, 3, 4, 5}
# the value of dynamic array dyn2 is '{1, 2, 3, 4, 5}
# dyn1 after change of dyn2 is '{1, 2, 3, 4, 5}
# dyn2 after change of dyn2 is '{1, 2, 10, 4, 5}
# dyn1 after new[10] is '{0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
# dyn2 after new[10] is '{1, 2, 10, 4, 5}
# dyn1 after new[10](dyn2) is '{0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
# dyn2 after new[10](dyn2) is '{1, 2, 10, 4, 5, 0, 0, 0, 0, 0}
I am not able to understand why after dyn2[2]=10
, when I display dyn1
, the print says
'{1, 2, 3, 4, 5}
and not
'{1, 2, 10, 4, 5}
on the simulator as I expect dyn1
and dyn2
to share the same memory and any change in dyn2
to be reflected into dyn1
.
Could you please explain the behavior in the simulation?
2 Answers 2
I expect dyn1 and dyn2 to share the same memory
The IEEE Std 1800-2023 does not specify that 2 separate dynamic arrays, when assigned to one another, will share the same memory.
Refer to section 7.6 Array assignments:
Assignment shall be done by assigning each element of the source array to the corresponding element of the target array. Correspondence between elements is determined by the left-to-right order of elements in each array. For example, if array
A
is declared asint A[7:0]
and arrayB
is declared asint B[1:8]
, the assignmentA = B;
will assign elementB[1]
to elementA[7]
, and so on.
The simulator behaves as expected according to the Std.
Unlike C/C++, arrays are not treated as pointers to memory. They are aggregate unpacked array types (or dynamic collections of identically typed elements). Every place you do an assignment to a dynamic array as a whole array, you are allocated a new space for that array, and then copying each element from source to destination. This is opposed to doing an assignment to a select of an array like yn2[2] = 10;
where there is no allocation.
Note that doing
dyn1 = new[5];
is not necessary before
dyn1 = '{1,2,3,4,5};
since that assignment does allocation prior to population of the array. It would be a tool optimization to figure out that the array has already been allocated to the needed size.