SystemVerilog: How to give different parameters to modules in the same array?

Question

In my design, I wanted to use a number of counters with different initial values on reset. Therefore I defined the counter module as follows:

module my_counter #(parameter int INIT_VALUE = 0)
 (
 input clock, reset,
 ...

Then in the design I have 4 instances of mycounter that share a lot of inputs, but have different initial values. I'd like to make them a module array, but the best way I've come up with is:

defparam my_counters[0].INIT_VALUE = 0;
defparam my_counters[1].INIT_VALUE = 1;
defparam my_counters[2].INIT_VALUE = 2;
defparam my_counters[3].INIT_VALUE = 3;
my_counter my_counters[3:0](
 .clock(clock),
 ...

That works with simulation, but I've heard that defparam is considered poor form. Furthermore, when trying to synthesize my design, the synthesizer complains that Syntax error at or near token '['. on the lines with defparam.

How could I do what I wanted to do without a lot of code duplication?

Answer 1

Use a generate loop

for(genvar ii=0; ii<4; ii++) begin : counter_loop
 my_counter #(.INIT_VALUE(ii)) my_cnt (.clock, .reset ... );
end : counter_loop

If the values you want to override cannot be computed by a simple loop expression, you can use a parameter array.

parameter int ARRAY_VALUE[4] = {1,3,5,10};
for(genvar ii=0; ii<4; ii++) begin : counter_loop
 my_counter #(.INIT_VALUE(ARRAY_VALUE[ii])) my_cnt (.clock, .reset ... );
end : counter_loop

• Imperishable Night: I usually shy away from generate loops due to the foreign syntax, but this seems to be the "correct" way to generate similar modules with different parameters. Thanks!
• Imperishable Night: Although in my case I ended up changing the "parameters" into constant inputs, because they are only used for initialization, and it struck me that if I wire an input to an constant, after synthesis it will just be hard-wired as I intended to... right?
• Greg: @Imperishable it will be hardwired. However if you preserve hierarchy in synthesis (common practice but no necessary default) then it can negativity impact your routing. You will likely have synthesis issues if these hardwired inputs are used as asynchronous reset/preset values. That said, there are situations where hardwired inputs have an advantage over parameters. It takes practice and some experimentation to figure out which approach works best for your current design.