Verilog set bit counter

Question

I'm trying to create a Verilog program that would display the digit with greater number of bits set. The code is working. However, it counts the bits from the previous values instead of its current value.

module compare_numbers(A,countA, B, countB, greaterA, greaterB, equalAB);
 input [7:0] A, B;
 output greaterA, greaterB, equalAB;
 output reg [7:0] countA, countB;
 
 integer i, j;
 
 
 always@(A)
 begin
 countA=0;
 for (i=0; i<9; i=i+1)
 if (A[i] == 1'b1)
 countA = countA + 1;
 end
 
 always@(B)
 begin
 countB=0;
 for (j=0; j<9; j=j+1)
 if (B[j] == 1'b1)
 countB = countB + 1;
 
 end 
 assign greaterA = (countA > countB);
 assign greaterB = (countA < countB);
 assign equalAB = (countA==countB);
endmodule
module tb;
 // Inputs
 reg [7:0] A, B;
 reg [255:0] string1;
 
 // Outputs
 wire greaterA, greaterB, equalAB;
 wire [7:0] countA, countB;
 
 
 compare_numbers tb(A,countA, B, countB, greaterA, greaterB, equalAB);
 
 initial fork
 $display("A\t\tB\t\tA no. of set bits\tB no. of set bits\tWhich has more bits set?");
 $monitor("%b\t%b\t%d\t\t\t%d\t%s",A, B, countA, countB, string1);
 join
 initial begin
 
 #1 A=8'b00001000; B=8'b11111110;
 if (greaterA==1) string1="Binary Digit A";
 else if (greaterB==1) string1="Binary Digit B";
 else string1="Equal digits";
 
 #3 A=8'b10001100; B=8'b10001100;
 if (greaterA==1) string1="Binary Digit A";
 else if (greaterB==1) string1="Binary Digit B";
 else string1="Equal digits";
 
 #5 A=8'b10101010; B=8'b00011000;
 if (greaterA==1) string1="Binary Digit A";
 else if (greaterB==1) string1="Binary Digit B";
 else string1="Equal digits";
 
 end

Error

Answer 1

The problem is due to a Verilog simulation race condition. You are trying to display values as they are changing. One solution is to add delays between when the signals change and when you call $monitor.

Here is a modified version of the testbench which calls $display when all the signals are stable. It adds a #1 delay before it sets string, then adds another #1 delay before it displays all the values:

module tb;
 // Inputs
 reg [7:0] A, B;
 reg [255:0] string1; 
 // Outputs
 wire greaterA, greaterB, equalAB;
 wire [7:0] countA, countB; 
 
 compare_numbers tb(A,countA, B, countB, greaterA, greaterB, equalAB);
 
 initial begin
 $display("A\t\tB\t\tA no. of set bits\tB no. of set bits\tWhich has more bits set?");
 
 #1 A=8'b00001000; B=8'b11111110; #1;
 if (greaterA==1) string1="Binary Digit A";
 else if (greaterB==1) string1="Binary Digit B";
 else string1="Equal digits";
 print();
 
 #3 A=8'b10001100; B=8'b10001100; #1;
 if (greaterA==1) string1="Binary Digit A";
 else if (greaterB==1) string1="Binary Digit B";
 else string1="Equal digits";
 print();
 #5 A=8'b10101010; B=8'b00011000; #1;
 if (greaterA==1) string1="Binary Digit A";
 else if (greaterB==1) string1="Binary Digit B";
 else string1="Equal digits";
 print();
 end
 task print;
 #1;
 $display("%b\t%b\t%d\t\t\t%d\t%s",A, B, countA, countB, string1,,$time);
 #1;
 endtask
endmodule

Output:

A B A no. of set bits B no. of set bits Which has more bits set?
00001000 11111110 1 7 Binary Digit B 3
10001100 10001100 3 3 Equal digits 9
10101010 00011000 4 2 Binary Digit A 17

Note that the code also displays the simulation time using $time. This is very useful for debug.