Verilog counter does not work

Question

I've written this code for a counter, but I don't know why it doesn't work. The output remains at zero, and when I change load to 0, output changes to unknown.

Would you please help me to find the error?

module behav_counter( d, clk, clear, load, up_down, qd);
 input [7:0] d;
 input clk;
 input clear;
 input load;
 input up_down;
 output [7:0] qd;
 reg [7:0] cnt;
always @ (posedge clk or negedge clear)
if (!clear)
 cnt = 8'h00;
else if (load)
 cnt = d;
else if (up_down)
 cnt = cnt + 1;
else
 cnt = cnt - 1;
assign qd = cnt;
endmodule
module test_b;
 reg d,clk,clear,load,up_down;
 wire qd;
 behav_counter bc( d, clk, clear, load, up_down, qd);
 initial
 begin
 clear = 0;
 clk = 0;
 #15 clear = 1; 
 repeat (400)
 #5 clk = ~clk;
 end
 initial 
 begin
 up_down=1;
 load=1;
 d=8'h00;
 #23
 load=0;
 #100
 load=1;
 end
endmodule

Answer 1

When I run your code on 2 different simulators, I get compile warnings about port size differences for d and qd. Your counter declares them as 8-bit wide, but you connect 1-bit signals to them. If you don't get warnings, try it on edaplayground.

In test_b, declare them as 8-bit:

module test_b;
 reg clk,clear,load,up_down;
 reg [7:0] d;
 wire [7:0] qd;

Now I see qd[7:0] count up from 0 to 0xa when load=0.