Is there any restriction on the maximum size of a SystemVerilog packed array?

Question

Suppose I make a packed array as:

logic [x:0] packed;

As packed arrays guarantee continuous memory allocation, is there any restriction on the maximum value x can take?

Answer 1

Generally not for simulation, although if you store very large arrays it will eventually bog down the simulation, the OS, or the machine. The limiting factor here will be the amount of memory available on the host running the simulation and its allocation limits.

Here is an example

module tb ();
 // localparam WIDTH = 500000; produces an os seg fault
 localparam WIDTH = 50000;
 logic [WIDTH - 1 :0] temp1;
 logic [WIDTH - 1 :0] temp2;
 
 initial begin
 temp1 = '1;
 assign temp2 = temp1;
 $display("%d",temp2);
 end
endmodule

This code printed a big number for WIDTH = 50000 but seg faulted after about 30 seconds for WIDTH = 500000 in Cadence on EDA Playground.

For synthesis flows, you are limited by the amount of physical memory available in the device that synthesis is targeting. The max size will depend on what you are modeling (constants, registers, memory or combinational logic) and how much of that resource the part has. Vivado synthesis will run, then report at the end that a particular resources in >100% utilized. Place and route (implementation) will fail.

The smallest Xilinx 7-series part has 10 18K-by-1 BRAMs reference Xilinx DS180, page 2. So you could potentially store a single packed vector of 180K bits in that part. Or you could store two 90K packed vectors or..... up to the limit of 180K bits total in that part.

The parts tend to get hard to implement after some percent utilization, usually 85%-95% depending on what else is in the part. Don't expect 100% utilization of physical resources when building in synthesis flows for FPGAs.