Systemverilog size attributes

Question

Suppose we have a 2d Systemverilog array declared as:

logic x [0:3][7:0] ;

1. How can we use an attribute to get the width of the first dimension ?
2. How can we use an attribute to get the width of the second dimension ?
3. Is there an attribute equivalent to VHDL's "range" attribute ? I.E: one that'll return not the size but the actual range ( 0 to 3 ) or ( 7 down to 0 ) ?

Answer 1

The IEEE Std 1800-2017, section 20.7 Array query functions, describes all that you need:

module tb;
logic x [0:3][7:0] ;
initial begin
 for (int i=1; i<=$dimensions(x); i++) begin
 $display;
 $display($size (x, i));
 $display($left (x, i));
 $display($right(x, i));
 $display($low (x, i));
 $display($high (x, i));
 $display;
 end
end
endmodule

Outputs:

 4
 0
 3
 0
 3
 8
 7
 0
 0
 7

See also System Tasks And Functions Part-II

• shaiko: Is IEEE Std 1800-2017 freely available ? If yes, where can it be download ?
• dave_59: @shaiko Click on the IEEE Get Program