I'm using Systemverilog interfaces to enable the implementation of generic functions. The interface is defined in one file as follows:
interface interface_onehot_to_binary
# (parameter WIDTH_ONEHOT=16)
(); // Empty port list
localparam WIDTH_BINARY = $clog2 (WIDTH_ONEHOT) ;
function logic [WIDTH_BINARY-1:0] onehot_to_binary
(logic [WIDTH_ONEHOT-1: 0] onehot);
automatic logic [WIDTH_BINARY-1:0] binary=0;
foreach (onehot[index])
begin
if (onehot[index]==1'b1) begin
binary=binary|index;
end
end
return binary;
endfunction
endinterface
And then instantiated in another file as follows:
interface_onehot_to_binary
#(.WIDTH_ONEHOT(256))
inst_interface_onehot_to_binary
(); // Empty port list
The simulation and synthesis tools that I use digest this code without issues. But the SpyGlass linter fails with the following error message: interface 'interface_onehot_to_binary' declaration does not have a modport definition. The error points to the first file - where the interface is defined. What's wrong with my code? How can it be solved?
1 Answer 1
class class_onehot_to_binary
# (parameter WIDTH_ONEHOT=16);
localparam WIDTH_BINARY = $clog2 (WIDTH_ONEHOT) ;
static function logic [WIDTH_BINARY-1:0] onehot_to_binary
(logic [WIDTH_ONEHOT-1: 0] onehot);
logic [WIDTH_BINARY-1:0] binary=0;
foreach (onehot[index])
begin
if (onehot[index]==1'b1) begin
binary=binary|index;
end
end
return binary;
endfunction
endclass
Note that even though onehot_to_binary
has a static class qualifier, the function has an automatic lifetime.
You would call this using class_onehot_to_binary#(32)::onehot_to_binary(value)
-
\$\begingroup\$ Thanks! If the class is declared in a package - shouldn't we call it as some_pkg::class_onehot_to_binary#(32)::onehot_to_binary(value) ? \$\endgroup\$shaiko– shaiko2021年02月20日 12:39:42 +00:00Commented Feb 20, 2021 at 12:39
interface
. Why not put your function in apackage
? \$\endgroup\$