Interface definition in package in SystemVerilog

Question

I have a very simple interface definition in a package in SystemVerilog:

1 package general_pack;
2 interface diff_i_t ( input p,
3 input n );
4 endinterface
5 endpackage

I added the file into a Vivado project, and then the editor shows an error at line 2:

Error: Syntax error near diff_i_t.

What's wrong with it? Is this the right way to define interfaces in a package?

Answer 1

It is illegal to declare an interface inside a package. You need to declare it outside the package:

interface diff_i_t ( input p,
 input n );
endinterface
package general_pack;
endpackage

Refer to IEEE Std 1800-2017, section 26.2 Package declarations:

SystemVerilog packages provide an additional mechanism for sharing parameters, data, type, task, function, sequence, property, and checker declarations ...

Other simulators provide a more helpful error message:

Error-[USVSNM] Unsupported SystemVerilog construct
 Found 'interface' inside package before 'endpackage'. 'interface' inside 
 'package' is not allowed.

The above message is from Synopsys VCS, which is available (along with other simulators) on EDA Playground.

• fiedel: Good to know that. I thought in VHDL way that put such shared definitions inside packages. But if it's outside a package, how do I refer to it in a different file?
• fiedel: OK, I saw someone mentioned an interface should be treated like a module and no need to include the definition like a package, just "instantiate" it.
• toolic: @fiedel: Yes, in that respect, think of an interface more like a module.
• fiedel: Got it. Thank you. @toolic