Multiple wire type objects declaration Verilog

Question

I get an error everytime I try to use the same line to declare more than one wire type, is this because they are of different size (but I get the error even when they're of the same size, declaring inputs)? When can I use the same line and declare multiple signals? (I am using SystemVerilog in QuestaSim)

wire [9:0]p1, [4:0]p2;

OR

input [5:0]p1, [5:0]p2;

Error Message (Vlog 13069) : enter image description here

Answer 1

I figured this out. If your module declaration lists the names of the ports within () and ends in a ; after which each of the ports are declared as input or output, then it has to be done one at a time. Also, only same sized objects of the same type can be declared with a comma, mentioning the size only once. The following example clarifies this,

module example1(a,b,c); //This kind of declaration
input a; //Needs each port declared separately
input b;
output c;
wire X,Y; //Acceptable, both X and Y are one bit wide
wire [5:0]p1,p2; //acceptable, both p1 and p2 are 6 bits wide