(vcom-1136) Unknown identifier "std_logic" & "std_logic_vector"

Question

I am relatively new to VHDL, and I am getting the errors below although I used the same procedure before:

vcom -work work -2002 -explicit -vopt -stats=none 
Questa Intel Starter FPGA Edition-64 vcom 2021.2 Compiler 2021.04 Apr 14 2021
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package NUMERIC_STD
-- Loading package MATH_REAL
-- Loading package std_logic_arith
-- Loading package STD_LOGIC_UNSIGNED
-- Compiling entity testbench_pack
-- Compiling package testbench_package
** Error: (vcom-1136) Unknown identifier "std_logic".
** Error: (vcom-1136) Unknown identifier "std_logic".
** Error: (vcom-1136) Unknown identifier "std_logic_vector".
** Error: (vcom-1136) Unknown identifier "std_logic_vector".
** Note: VHDL Compiler exiting

The code:

library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use ieee.STD_LOGIC_ARITH.ALL;
use ieee.STD_LOGIC_UNSIGNED.ALL;
entity testbench_pack is
end testbench_pack;
package testbench_package is
 procedure assert_floor_and_door(
 constant clock : in std_logic;
 constant reset : in std_logic;
 variable floor : in std_logic_vector(2 downto 0);
 variable door : in std_logic_vector(1 downto 0)
 );
 
end package testbench_package;
package body testbench_package is
 procedure assert_floor_and_door(
 constant clock : in std_logic;
 constant reset : in std_logic;
 variable floor : in std_logic_vector(2 downto 0);
 variable door : in std_logic_vector(1 downto 0)
 ) is
 variable door_s_int : natural;
 variable floor_int : natural;
 begin
 -- Procedure code here...
 -- Convert door to integer
 door_s_int := to_integer(unsigned(door));
 -- Convert floor to integer
 floor_int := to_integer(unsigned(floor));
 -- Assertion for floor value
 assert floor_int >= 0 and floor_int <= 7
 report "Assertion failed for floor value: " & integer'image(floor_int)
 severity failure;
 -- Assertion for door value
 assert door_s_int >= 0 and door_s_int <= 3
 report "Assertion failed for door value: " & integer'image(door_s_int)
 severity failure;
 end procedure;
end package body testbench_package;
architecture Behavioral of testbench_pack is
 signal s_clock : std_logic := '0';
 signal s_reset : std_logic := '0';
 signal s_floor : std_logic_vector(2 downto 0) := "000";
 signal s_door : std_logic_vector(1 downto 0) := "00";
begin
 process
 begin
 wait for 5 ns;
 s_reset <= '1';
 wait for 10 ns;
 s_reset <= '0';
 wait;
 end process;
 process
 begin
 wait for 2 ns;
 s_clock <= not s_clock;
 wait for 2 ns;
 end process;
 process
 begin
 wait for 20 ns;
 s_floor <= "001";
 s_door <= "01";
 wait for 10 ns;
 s_floor <= "010";
 s_door <= "10";
 wait for 10 ns;
 s_floor <= "111";
 s_door <= "11";
 wait;
 end process;
 process
 begin
 wait for 5 ns;
 testbench_package.assert_floor_and_door(s_clock, s_reset, s_floor, s_door);
 wait;
 end process;
end Behavioral;

Answer 1

You can overcome these errors by moving the package code into its own file and compiling both files in your compile command.

This EDA Playground link demonstrates your code compiling without errors.

You also need to use your testbench_package package in the testbench_pack file:

library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use ieee.STD_LOGIC_ARITH.ALL;
use ieee.STD_LOGIC_UNSIGNED.ALL;
use work.testbench_package.all;
entity testbench_pack is
end testbench_pack;

Answer 2

The scope of library and use extends only until the end of the current design unit, which is the entity declaration. If you add an architecture for the same entity, you can also use the imported names there, because these are visible through the entity.

The package is its own design unit though, and needs its own set of library and use clauses. Typically, that is done at the beginning of a separate file.