Is it inefficient or bad style to build std_logic_vector out of std_logic inputs?

Question

I'm learning VHDL, and there are a lot of exercises where they give you an entity and you have to write the architecture, where a lot of the inputs are separate:

entity m is port (
 A, B, C: in std_logic;
 Y: out std_logic);
end m;

Now I could try to come up with some combination of operations but I find it pretty easy to just make lookup tables:

architecture b of m is
 signal together : std_logic_vector(2 downto 0);
begin
 together <= A & B & C;
 -- now do: "with together select" and then write out all the possibilities
end architecture b;

Is this bad style? Does the creation of the "together" signal cost anything or is the compiler going to synthesize the same thing it would dealing with A, B, C separately? I'm basically only making the vector so I can match on all 3 values at once.

• DKNguyen: I don't know about bad style but certain things are major PITA or very clunky to do unless they are std_logic_vectors. I made an entity that turns multiple std_logic into std_logic vectors for that purpose. It was for operating flags where it made more sense to set the different functions per bit since conceptually it made more sense to do it that way for the person using it. However, under the hood dedicated logic was required for each combination of flags (things weren't didn't operate as independently as it seem) so it was much less clunky to check the operating mode as a std_logic_vector.
• Mitu Raj: Looks unneccesarily cumbersome even though both have the same result in synthesis.
• user16324: Nothing wrong with it, commonly used and works.

Answer 1

Style

I'd never let this pass through code review, but not because you want to write a lookup table. Combinatorial logic definition using signals was relevant in the 1980s, but we're 4 decades later now. The whole concatenation/lookup really belongs in a process, like so:

p_main: process(a, b, c)
 variable together : std_logic_vector(2 downto 0);
begin
 together := a & b & c;
 case together is
 when whatever =>
 do things;
 end case;
end process;

Which allows you to write VHDL the way you'd write software, with instant variable updates and no need to take into account delta cycles/update scheduling. The whole thing will run one time each time a, b, c or a combination of them updates, and the sequential order in which everything runs is easily determined, can be easily debugged and whatever you want.

Synthesis efficiency

Your adjustment won't matter for synthesis, you'll get the same hardware whether you do your concatenation or not. (For larger signals, the synthesis tool will even prefer your style because it allows for larger optimization branches, but even then the effect won't be noticeable).

Simulation efficiency

is what you potentially sacrifice, you basically introduce one extra delta cycle of simulation time. A change on a, b, c or a combination will first trigger a change on the together signal and only then trigger your lookup table.

Will you notice this? Probably not.

Is it worth taking into account? No, never, unless it convinces you to write a process.

• user8352: There's a requirement that the subtype of the case expression be locally static you've addressed by using the variable together. That can also be satisfied without the variable - subtype together is std_logic_vector(2 downto 0); and in the case expression case together'(a & b & c) is using a qualified expression. Whose code review? Style is superimposed organizationally.
• DonFusili: @user8352 Agreed, code reviews at my job, then.

Answer 2

First of all it's not bad at all to build std_logic_vectors out of std_logic. Whether I'd prefer lookup tables over normal logic is another question because usally you wouldn't name your signals a, b and c but give them some meaningful names. If you enpack your logic into a lookup table it might becomes intransparent to who ever has to read your code.