VHDL synthesize std_logic 'H'

Question

Can the weak-pullup 'H' assignment of std_logic be synthesized, or is it only allowed in simulation? You're probably wondering why I would want to do this: I'm trying to emulate both the master and slave I2C devices inside the same FPGA (internal bi-directional bus), thus I have no external pull-up resistor. I'm not sure what input logic level the FPGA will see when both master and slave are set to 'Z'. I realize that since both devices are inside the FPGA, I could just avoid using the bi-directional buffer, but I'd like to be able to use the same exact i2c master code, as is, and at a later time route it to real hardware.

• Mitu Raj: As far as I know, it's just a simulation model for pull ups. Not synthesisable.

Answer 1

There won't be a universal answer except "no".

But check the synthesis guide for your chosen FPGA in case it is an exception (can synthesise 'H' to an internal pullup).

You'd be better treating the output and input aspects separately on your cores (SDAout/SDAin) and combining both/all SDAouts (which are '0' or '1') in logic gates in the top level design, and feeding the result to all SDAins. (Ditto SCL to handle clock stretching).

This mimics the strategy of avoiding bidirectional internal buses with Data_Out/Data_In buses and multiplexing in the top level design.