Verilog error: cannot be driven by primitives or continuous assignment

Question

Please someone explain why I am getting below error from this code:

module data_path(A, B, Product, clr, rsh, addsub, pld, ld, done, clk, count1, temp, alu);
input signed [4:0] A, B;
output reg signed [9:0] Product;
input clr, rsh, pld, ld, done, clk, alu;
input [1:0] addsub;
output [2:0] count1;
wire [2:0] count1;
wire signed [4:0] M;
wire [9:0] data, data_alu;
output reg [1:0] temp;
PIPO p1(A, B, data, count1, M, clr, clk, ld, temp);
ALU a1( data, clr, clk, addsub, temp, count1, alu, M, data_alu);
rightshift r1(clk, rsh, data_alu, Product, clr);
endmodule
module PIPO(A, B, data, count0, M, clr, clk, ld, temp);
input signed [4:0] A, B;
input ld, clr, clk;
output reg [9:0] data;
output reg signed [4:0] M;
output reg [2:0] count0;
output reg [1:0] temp;
reg f_bit;
always @(posedge clk)
if(clr)
begin
 data <= 10'b0;
 temp <= 2'b0;
 count0 <= 3'b0;
 M <= 5'b0;
 end
 else if(ld)
 begin
 data[4:0] <= B;
 data[9:5] <= 5'b0;
 assign f_bit = 1'b0;
 temp <= {B[0],f_bit};
 M[4:0] <= A[4:0];
 count0 <= 3'b0;
end
endmodule
// addition subtration
module ALU( data, clr, clk, as, temp, count0, alu, M, Product);
input [1:0] as;
input clr, clk, alu;
input [9:0] data;
input [4:0] M;
output reg [2:0] count0;
output reg [1:0] temp;
output reg signed [9:0] Product;
always@(posedge clk)
begin
 if(alu==1) 
 begin
 case(as) 
 2'b00: Product[9:5] <= data[9:5] + M[4:0]; 
 2'b01: Product[9:5] <= data[9:5] - M[4:0];
 2'b10: Product <= data;
 default: begin
 end
 endcase 
 count0 <= count0 + 1;
 temp <= {Product[1], Product[0]};
 end
 else if(clr==1) Product <= 10'b0;
end
endmodule
module rightshift(clk, rsh, data, Product, clr);
input clk, rsh, clr;
input [9:0] data;
output reg [9:0] Product;
always@(posedge clk)
if(clr==1)
Product = 10'b0;
else if(rsh==1)
 Product = {data[9], data[9:1]};
endmodule

Errors:

main.v:12: error: reg temp; cannot be driven by primitives or continuous assignment.
main.v:12: error: Output port expression must support continuous assignment.
main.v:12: : Port 9 (temp) of PIPO is connected to temp
main.v:13: error: reg temp; cannot be driven by primitives or continuous assignment.
main.v:13: error: Output port expression must support continuous assignment.
main.v:13: : Port 5 (temp) of ALU is connected to temp
main.v:14: error: reg Product; cannot be driven by primitives or continuous assignment.
main.v:14: error: Output port expression must support continuous assignment.
main.v:14: : Port 4 (Product) of rightshift is connected to Product
6 error(s) during elaboration.

Answer 1

You must not declare temp or Product as reg type. Simply remove the reg keyword from the module port declarations for those 2 signals. This code compiles without errors:

module data_path(A, B, Product, clr, rsh, addsub, pld, ld, done, clk, count1, temp, alu);
input signed [4:0] A, B;
output signed [9:0] Product;
input clr, rsh, pld, ld, done, clk, alu;
input [1:0] addsub;
output [2:0] count1;
wire [2:0] count1;
wire signed [4:0] M;
wire [9:0] data, data_alu;
output [1:0] temp;
PIPO p1(A, B, data, count1, M, clr, clk, ld, temp);
ALU a1( data, clr, clk, addsub, temp, count1, alu, M, data_alu);
rightshift r1(clk, rsh, data_alu, Product, clr);
endmodule

Answer 2

The key part is:

reg cannot be driven by ... continuous assignment.

Variables declared as type reg can only be assigned in procedural blocks, they cannot be connected to our ports of a submodule.

For example you have output reg temp and try to drive it from the output port of submodule PIPO:p1.temp. Instead you should have output temp in your data_path module (the same for Product).

---

You also have a second problem - you are driving the temp signal in the data_path module from both the ALU and PIPO module outputs. This is not possible, the signal should have one source, so you'll need to fix that too.