Verilog simulation unexpected behaviour in a simple mux design (Using EDAPlayground and EPWave)

Question

I am experimenting with EDAPlayground, and I have created a simple structural module that should take the MSBs from one input and merge it with the LSBs of the other and vice versa, using 2 input multiplexers. Here is the .sv code:

module mux2(input logic [3:0] d0, [3:0] d1, s,
 output logic [3:0] y);
 assign y = s ? d1 : d0;
 
endmodule
module mux2_8(input logic [7:0] d0, [7:0] d1, s,
 output logic [7:0] y);
 
 mux2 muxHigh(d0[7:4],d1[7:4],s,y[7:4]);
 mux2 muxLow(d0[3:0],d1[3:0],~s,y[3:0]);
 
endmodule

And here is the testbench:

module testBench();
 
 logic[7:0] tbD0;
 logic[7:0] tbD1;
 logic tbS;
 logic[7:0] tbY;
 
 mux2_8 MuxDUT(tbD0,tbD1,tbS,tbY);
 
 initial begin
 
 #1;
 tbD0='b10101111;
 tbD1='b11110101;
 tbS=1;
 
 #1;
 tbS=0;
 
 #1;
 tbS=1;
 
 #1;
 tbD0=0;
 $finish();
 
 end
 
 initial begin
 $dumpfile("dump.vcd");
 $dumpvars;
 end
 
endmodule

When s is 0, I get the expected output: MSB from d0 and LSB from d1 (10100101). But, when s changes to 1, the output becomes d1 (11110101). The correct result should be 11111111 when s=1.

Answer 1

In mux2_8, you mistakenly declared the s input port as 8 bits wide, but you really want it to be 1-bit wide. In the following line:

module mux2_8(input logic [7:0] d0, [7:0] d1, s,

the second range specifier, [7:0], applies to all signals after it: d1 and s. Refer to IEEE Std 1800-2017, section 23.2.2.3 Rules for determining port kind, data type, and direction:

For subsequent ports in an ANSI style port list: — If the direction, port kind and data type are all omitted, then they shall be inherited from the previous port.

One way to fix this problem is to add the input keyword just before s:

module mux2_8(input logic [7:0] d0, [7:0] d1, input s,

The same problem occurs with the mux2 module. Change it to:

module mux2(input logic [3:0] d0, [3:0] d1, input s,

Here is the fixed code:

module mux2(input logic [3:0] d0, [3:0] d1, input s,
 output logic [3:0] y);
 assign y = s ? d1 : d0;
 
endmodule
module mux2_8(input logic [7:0] d0, [7:0] d1, input s,
 output logic [7:0] y);
 
 mux2 muxHigh(d0[7:4],d1[7:4], s,y[7:4]);
 mux2 muxLow (d0[3:0],d1[3:0],~s,y[3:0]);
 
endmodule

When I run your code on EDAPlayground, I see warning messages that directly point to these signal width mismatches. I see messages on 4 different simulators. For example:

Warning-[PCWM-W] Port connection width mismatch
testbench.sv, 24
"mux2_8 MuxDUT(tbD0, tbD1, tbS, tbY);"
 The following 1-bit expression is connected to 8-bit port "s" of module 
 "mux2_8", instance "MuxDUT".
 Expression: tbS
 Instantiated module defined at: "testbench.sv", 8
 Use +lint=PCWM for more details.

Another visual clue that there was a problem was that the signal showed up as s[3:0] in the waveforms of the muxHigh instance.