How do I instantiate modules within case statements in Verilog HDL?

Question

I am trying to make a sequence detector with 4 modes - Moore machine overlapping & non-overlapping and Mealy machine overlapping & non-overlapping.

But writing my code like this gives me an error:

module seq_det(
 input clk, rst_n, x,
 input [1:0] mode,
 output reg z
);
 
 case (mode)
 2'b00: moore_det_nonov SD1(clk, rst_n, x, z);
 2'b01: moore_det_ov SD2(clk, rst_n, x, z);
 2'b10: mealy_det_nonov SD3(clk, rst_n, x, z);
 2'b11: mealy_det_ov SD4(clk, rst_n, x, z);
 endcase
endmodule

Here I have made 4 modules separately which I am trying to instantiate. Here's one of them, others are similar:

module mealy_det_ov(input clk, rst_n, x, output reg z);
 parameter A = 4'h1;
 parameter B = 4'h2;
 parameter C = 4'h3;
 parameter D = 4'h4;
 
 reg [3:0] curr_state, next_state;
 always @(posedge clk or negedge rst_n) begin
 curr_state <= rst_n ? next_state : A;
 end
 
 always @(curr_state or x) begin
 case(curr_state)
 A: next_state <= x ? B : A; 
 B: next_state <= x ? B : C;
 C: next_state <= x ? D : A;
 D: next_state <= x ? B : C;
 default: next_state = A;
 endcase
 end
 always @(curr_state) begin
 z <= (curr_state == D) ? 1:0;
 end
endmodule

I know what I am doing is wrong, so please point me in the right direction.

Answer 1

You need four instances and a mux to switch the output between them.

If you instantiate this with mode set to a fixed value, the optimizer will remove those instances that are never connected to the output.

Answer 2

In the end I used conditional compilation and execution to instatiate the required module by defining the mode as a macro instead of an input.