Do case statements inside a for loop work in verilog?

Question

I am doing a code for radix-4 booth encoding for 8*8 multiplication. The logic is correct and there are no errors or warning. The output am getting is totally unrelated. i have posted the code below

module comp8mul (a, b, outc, clk);
 input [7:0] a, b;
 input clk;
 output [4:0] outc;
 wire [8:0] a1;
 reg [8:0] a12;
 wire [11:0] b1;
 integer i;
 reg [2:0] c1;
 reg [11:0] ou1;
 reg [4:0] b11 [0:11];
 reg [4:0] s1;
 assign a1 = {1'b0,a};
 assign b1 = {1'b0,b,1'b0,1'b0};
 always @(posedge clk) begin
 for (i=11; i>=2'd2; i=i-(2'd2)) begin:rloop
 c1={b1[i-2'd2],b1[i-1'b1],b1[i]};
 case(c1)
 3'b000: begin
 ou1=11'b0;
 s1[(i-(2'd3))/2'd2]=1'b0;
 end
 3'b001: begin
 ou1=a1;
 s1[(i-(2'd3))/2'd2]=1'b0;
 end
 3'b010: begin
 ou1=a1;
 s1[(i-2'd3)/2'd2]=1'b0;
 end
 3'b011: begin
 a12=a1<<1;
 ou1=(~a12)+1'b1;
 s1[(i-(2'd3))/2'd2]=1'b1;
 end
 3'b100: begin
 a12=a1<<1'b1;
 ou1=(~a12)+1'b1;
 s1[(i-(2'd3))/2'd2]=1'b1;
 end
 3'b101: begin
 ou1=(~a1);
 s1[(i-(2'd3))/2'd2]=1'b1;
 end
 3'b110: begin
 ou1=(~a1);
 s1[(i-(2'd3))/2'd2]=1'b1;
 end
 3'b111: begin
 ou1=12'b0;
 s1[(i-(2'd3))/2'd2]=1'b0;
 end
 endcase
 if (((i-(2'd3))/2'd2)==3'd4) begin
 b11[((i-(2'd3))/(2'd2))]={(~s1[(i-(2'd3))/(2'd2)]),s1[(i-(2'd3))/(2'd2)],s1[(i-(2'd3))/2'd2],ou1};
 end
 if (((i-(2'd3))/(2'd2))==1'b1) begin
 b11[(i-(2'd3))/(2'd2)]={(~s1[(i-(2'd3))/(2'd2)]),ou1};
 end
 if(((i-(2'd3))/(2'd2))==1'b0) begin
 b11[((i-(2'd3))/(2'd2))]=ou1;
 end else
 b11[(i-(2'd3))/(2'd2)]={1'b1,(~s1[(i-(2'd3))/(2'd2)]),ou1};
 end
 end
 assign outc = b11[0];
endmodule

I should get five 12-bit partial products as outputs. I am assigning 1 row of the 2-d array to output and checking it.

• Wandering Logic: @twinkle: I can not figure out what you are asking. What is the output you are getting that seems unexpected to you?
• Martin Thompson: Show your testbench - what goes in, what comes out. What did you expect to get out?
• Tim: Yes, you can use a case statement inside a for loop. However you do realize that the entire for loop will execute instantaneously (all 12 loops on the first posedge clock), right?

Answer 1

If "five 12-bit partial products as outputs" desired, then reg [4:0] b11 [0:11]; should be reg [11:0] b11 [0:4];.

Your b11 calculation is likely incorrect. There are missing elses before many of the if statements. Therefore, all except the final if condition with fall into the final else condition. You need to nest the else-ifs. Alternatively ,you can use another case statement. Also you need to control the ou1 range otherwise the upper assigned bits will be out of range for b11 and masked out.

Suggestion: (i-2'd3)/2'd2 and format variations of the same equations is used many places. Assign it to a variable, such as reg [2:0] c2, and call the variable (c2) instead of the equation. c2 should be assigned just like your c1. This will help readability of the code and lower chances of a typo.