Synthesis output for the following verilog code

Question

I have a somewhat stupid question as I am still a noob. So bear with me.

If I have the following statement in Verilog:

input rdy,in;
reg o;
always @(posedge clk)
begin
 if (rdy) o<=in;
end

I am wondering what the synthesis output look like. Would a mux be instantiated in front of the D flip-flop by the synthesis tool?

In other words, is there a need for me to create a combinational block that take i, o and rdy as input and generate a temp signal that feeds the input of d flip flop?

• Mitu Raj: Not a stupid question at all...

Answer 1

There are two possibilities for Synthesiser to explore which may depend on the tool/optimizations used:

1. The reg o becomes a flip-flop with a 2:1 mux 'in front of it'. The two inputs of the mux will be: The input in and the output of reg o flip-flop fed back. And the mux will have rdy as select signal.

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2. The reg o becomes a flip-flop with rdy as clock enable. And in as the D input.

enter image description here

• hardware noob: Thanks for the fast reply. It seems the second option is more energy efficient , agree?
• Mitu Raj: That's right. The second pointer is what happens by default if I synthesise this on Vivado for Xilinx FPGAs.
• Elliot Alderson: I don't think you can look at the symbol for a clock-enable FF and infer that it is more energy efficient than adding a mux externally. If they are functionally equivalent then it is possible that they are also electrically equivalent, particularly in an FPGA. The second option might exist only for the convenience of drawing or looking at schematics.
• Mitu Raj: I think you got a point there. I just checked and found that flip-flops in the Xilinx library have CE pin always. It will be by default tied to '1' if RTL is written in such a manner that a mux is incorporated like in (1). But still, it's debatable about the overall power consumption because even though there is no mux anymore, now there will be switching activity at CE pins. @ElliotAlderson