What is scope of variables in Verilog modules?

Question

I am fairly new to Verilog and can’t find out if Verilog modules have same scope privacy as for example C functions have. For example can I use same name ( say clk ) for variables in different modules ?

Answer 1

Verilog has several name spaces for different kinds of constructs. See Section 3.13 Name spaces in the IEEE 1800-2017 SystemVerilog LRM.

Briefly, each module definition creates a name space for itself and you can declare variable with the same names within each module. There is no implicit connection between variables with the same name in different modules, you must connect them through ports. Within a module you can have other local scopes and declare variables with the same name inside them. (like inside a function)

You might want to read my DVCon paper about variable scopes and lifetimes.

Answer 2

Signals declared inside a module have their scope local to that module only. So, yes, two different modules in a source file can have signals with same name, with corresponding local scopes.

However, recommended coding practice - single module in a single source file.