verilog code with two falling edges

Question

Please look at the picture for this description. I have a problem with writing verilog for the following logic: Consider clk and R3 are input signals & out is the output signal. At the falling edge of clk, out is reset to 0. At the falling edge of R3, out is set to 1. How can I implement this logic in verilog? I am stuck because it seems to me that there is no way to distinguish between falling edge of R3 and falling edge of clk.

At the falling edge of both clk and R3, both clk and R3 are equal to 0 so I can't distinguish them.

 module startup(clk, R3, out); 
 input clk, R3; 
 output reg out; 
 always@(negedge clk, negedge R3) begin 
 end 
 endmodule

enter image description here

• Elliot Alderson: R3 and CLK are two different signals...of course you can distinguish between their falling edges. Show us the code that you have tried and explain why it didn't do what you expected.
• emnha: @ElliotAlderson I have just added above. I don't know how to continue because I can't distinguish them.
• Elliot Alderson: Possible duplicate of Verilog: Check for two negedges in always block
• Dave Tweed: Not right now. The design of ASMs is not trivial. Is there any chance that you could sample both input signals with a higher-speed clock and turn this into a synchronous problem?
• Dave Tweed: What's your target implementation technology? FPGAs are not well-suited to asynchronous design.

Answer 1

Each input requires its own process. Create two "toggle" FFs, and then XOR their outputs together. Toggle the "set" FF when the output is zero, and toggle the "reset" FF when the output is one.

module dual_edge_ff (
 input set,
 input reset,
 output q
);
 reg set_ff;
 reg reset_ff;
 assign q = set_ff ^ reset_ff;
 always @(negedge set) if (!q) set_ff <= !set_ff;
 always @(negedge reset) if (q) reset_ff <= !reset_ff;
endmodule

If you're building this with discrete logic, you just need a 74xx73 (dual negative edge triggered JK FF) and a 74xx86 (quad XOR gate, use one section as an inverter).

Answer 2

At the falling edge of clk, out is reset to 0. At the falling edge of R3, out is set to 1. How can I implement this logic in verilog?

First, you should consider whether your logic is realizable in the technology you're using. Since you are using Quartus, I'll assume you're targeting an FPGA or CPLD technology.

And the logic you're asking for is not a well known latch or flip-flop type, so you will not be able to implement it directly in an FPGA or CPLD.

A typical solution to this is to introduce a high-speed clock, maybe 10 or more times faster than any of your other signals, and use that to detect transitions in the original signals (code not tested)

module latch1 (input hsclk, 
 input clk, 
 input r3, 
 output out);
reg clka, r3a;
always @(posedge hsclk) begin
 clka <= clk;
 r3a <= r3;
end
always @(posedge hsclk) begin
 if (clka & ~clk) begin
 // Actions for falling edge of clk
 out <= 0;
 end
 if (r3a & ~r3) begin
 // Actions for falling edge of r3
 out <= 1;
 end
end
endmodule

Notice that if the falling edge of r3 and falling edge of clk occur within one cycle of hsclk of each other, then the r3 edge will take precedence. Choose the period of hsclk to minimize the risk of this happening.

• emnha: Thanks for the help but I don't have a higher clock available.
• The Photon: @anhnha, if your clk signal is actually a periodic clock, you could use the PLL in your FPGA to generate a high frequency clock from it. Otherwise, an FPGA is probably not a good solution to your problem.