Implementing 3 to 8 decoder using 4 input NOR Gate

Question

I have deduced the truth table to the required logic function, but I really need some advise on how I could implement it using a 3 to 8 line decoder, an inverter and a 4 input NOR Gate.

A3 A2 A1 A0 Z
0 0 0 0 0
0 0 0 1 1
0 0 1 0 X
0 0 1 1 0
0 1 0 0 X
0 1 0 1 1
0 1 1 0 0
0 1 1 1 1
1 0 0 0 X
1 0 0 1 0
1 0 1 0 X
1 0 1 1 1
1 1 0 0 0
1 1 0 1 1
1 1 1 0 X
1 1 1 1 0

• vicatcu: I'm very confused by this question + this title ... is the question how to implement this arbitrary logic function using only 3-to-8 decoders, 4-input NOR gates, and inverters?
• Ivan: Yes. However only a single 3 to 8 decoder and a 4 input NOR gate.
• vicatcu: is this homework? be honest...
• Ivan: i don't know what to try, there are 5 minterms, how am i can use a 4 input NOR gate? yes this is homework.
• Ivan: i've made a karnaugh map, not sure if that would be useful here.

Answer 1

The fact that you were given a NOR gate rather than an OR gate is a significant hint: Look for the patterns of zeros, rather than ones, in your K-map. And remember that don't-cares can be assigned the value zero or one.

Here's the K-map I came up with, based on your truth table:

 A0 0 0 1 1
 A1 0 1 1 0
A3 A2 +------------
0 0 | 0 x 0 1
0 1 | x 0 1 1
1 1 | 0 x 0 1
1 0 | x x 1 0

If you make all of the don't cares zero, you get this:

 A0 0 0 1 1
 A1 0 1 1 0
A3 A2 +------------
0 0 | 0 0 0 1
0 1 | 0 0 1 1
1 1 | 0 0 0 1
1 0 | 0 0 1 0

Clearly, the left-hand side of the table can be taken care of by feeding not-A0 (using the inverter you were given) into one input of the NOR gate.

The remaining three zeros (Aha!) can be taken from individual outputs of the 3-to-8 decoder, whose A, B and C inputs are connected to A1, A2 and A3, respectively. Specifically, the outputs for "1", "4", and "7" should be connected to the three remaining inputs of the NOR gate.

• Ivan: Hi, I've already done all that. Please see the comments in the above answer. I've already deduced the SOP. I need help on how to actually draw the 3-to-8 line decoder and make the connections with the inverter, 4-input NOR gate. thank you
• Ivan: nice. but where would an inverter be used?
• Ivan: smh please ignore that! lol. thx for the help! appreciated!

Answer 2

Start with this line of thinking...

A 3-to-8 decoder generates a binary signal that tells you which minterm it is being stimulated by. The don't care conditions give you some opportunities to minimize the logic. Use a K-MAP or similar technique to reduce the truth table to a boolean expression that is a product of maxterms... hint I can reduce that logic function to a four-term POS expression.

• Ivan: The SOP is: Z = A2A1'A0'+ A0A3'A2 + A3'A1'A0 + A3A2'A1. How can I go on from here?
• vicatcu: @Ivan how many 3-to-8 decoders can you use? You can do it trivially if you have 4 ... Each one gives you one minterm. Nor them all, and invert the output.
• Ivan: only a single 3-to-8 decoder, how could i go about doing that?
• Ivan: I will describe the question exactly as it is: "You are to design a combinational logic circuit with four inputs, A3, A2, A1 and A0, and one output, Z. The output should be: 0 when the decimal value of the binary number A3A2A1A0 is zero or divisible by three; 0 or 1 (i.e. don't care) when the decimal value of the binary number A3A2A1A0 is not divisible by three but is divisible by two; and 1 for all other inputs." (sounds complicated but you can draw up this truth table in 10 seconds)
• Ivan: Now after some follow up q's such as draw up the truth table, the following question is asked: "Implement the function using a standard 3-to-8 line decoder, an inverter and a 4- input NOR gate"