Implementing Logic Using 2x4 Decoder (Confusions with Non/Negated Inputs/Outputs)

Question

In a question, I'm asked to implement the below using a 2x4 Decoder with Negated Outputs and a Negated Enable

Truth table for the decoder was:

The given answer was the top diagram, mine the bottom:

How could it be the top? S3 = 1 when BC = 10 not 01?

How do you go about deciphering such logic, I find myself very confused when there are negated inputs/outputs

Answer 1

I may be wrong, but it looks like the A and B of the decoder truth table corresponds with B and C in the top table (A being wired to the enable)
In other words, the top tables A, B and C should be seen as signal names, rather than the names of pins on the decoder.
So signal B goes to pin A, signal C goes to pin B, and signal A goes to enable pin.
Maybe the original question was badly set out.

• Jiew Meng: Ok I updated my question as shown in the question.
• Oli Glaser: @jiewmeng - thanks, it looks to me like there is a mistake in the question or supplied answer, as input A high and B low is the only combination (when enabled) that can produce a 1 at S3.
• Jiew Meng: so my answer (bottom blue one) correct? btw, how would you go about solving this problem? I find myself very confused when theres negated inputs/outputs. what would you use to test these circuits out?
• Oli Glaser: @jiewmeng - no, your answer doesn't work for the lower half of the first table when enable (A) is high. For testing, I would probably just simulate in Verilog or another suitable tool (e.g. a mixed SPICE simulator should be fine) For solving this I would probably just think a bit, but you could apply things like karnaugh maps and/or logic reduction software.
• Oli Glaser: Sorry, I meant to include that I think the solution mentioned in my answer is the correct one (i.e. just the given answer with B and C swapped)