How to build a 3-input NAND gate from 2-input NAND gates or a 3-input NOR gate from 2-input NOR gate?

Question

For NAND, I am doing a truth table for it and then truth tables for all the possible combinations, but as you can see the process is very long and I am still yet to get an answer. Same goes for NOR gate. How do you go about it?

Answer 1

An alternate approach is given.

schematic

^{simulate this circuit – Schematic created using CircuitLab}

The schematic represents the function: $$Y = \overline{ABC} = \overline{\overline{\overline{AB}} C}$$

• studious: How did you find Step 2 from Step 1?
• nidhin: @studious \$Y=\mathtt{nand(A,B,C)} = \mathtt{not\{and(A,B,C)\} = \\ not\{and(and(A,B),C)\}=nand\{and(A,B),C\}}\$

Answer 2

As equations.

\$\overline{ABC} = \overline{(AB)C} = \overline{\overline{\bar A+\bar B}\cdot C}\$

• studious: Wow that's cool
• Ignacio Vazquez-Abrams: It's also something that should have been covered in Boolean Algebra 101.
• studious: First week of the semester and so on
• Tom Carpenter: Though to build that from NAND/NOR gates would take four gates in total. It can be done with just three gates. Notice that the \$(AB)\$ is a 2-input AND gate, which is equivalent to \$\overline{\overline{AB}}\$ which is a 2-in NAND gate followed by an inverter (another 2-in NAND with both inputs tied together). So \$\overline{ABC} = \overline{\overline{\overline{A \cdot B}}\cdot C}\$
• studious: Is there any other way to do this other than this?

Answer 3

Note that in the above answers, there are three propagation delays for A and B, but only one for C. Therefore, if propagation delays matter, put two nand gates in series in line C, wired as inverters.