How can I make Verilog HDL ModelSim test bench for a simple ripple adder circuit output an addition table instead of a long list of every calculation?

Question

I've completed my assignment and I'd like to make the output look something like this, with one table for sum output and one table for carry output:

Sum:
 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
 __ __ __ __ __ __ __ __ __ __ __ __ __ __ __
1 | 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
2 | 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
3 | 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
4 | 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
...
15| 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

Is this something that could be easily achievable?

Here's my main file, RCA.v:

module RCA(CIN,A,B,S,C);
 input CIN;
 input wire [3:0] A,B;
 output wire [4:0] S;
 output wire [3:0] C;
 
 CA bit0 (CIN, A[0], B[0], S[0], C[0]);
 CA bit1 (C[0], A[1], B[1], S[1], C[1]);
 CA bit2 (C[1], A[2], B[2], S[2], C[2]);
 CA bit3 (C[2], A[3], B[3], S[3], C[3]);
 assign S[4] = C[3];
endmodule
module CA(cIn,a,b,s,cOut);
 
 input a,b,cIn;
 output s,cOut;
 
 assign cOut = (a & b)|((a ^ b) & cIn);
 
 assign s = (cIn ^ (a ^ b));
 
endmodule 

And this is my current testbench file, tb_RCA.v:

`timescale 1ns / 1ps
module tb_RCA ();
 reg [3:0] A;
 reg [3:0] B;
 reg CIN;
 wire [4:0] S;
 wire [3:0] C;
integer i;
RCA uut (
 .A(A),
 .B(B),
 .S(S),
 .C(C),
 .CIN(CIN)
);
initial begin
 for(i=0; i < 2**8; i = i+1) begin
 {A,B} = i;
 CIN = 0;
 #5;
 $display( "%d + %d = %d | %d", A, B, S, C );
 #5;
 end
end
endmodule 

The testbench output looks like this right now, where the first two numbers are each number to be summed, followed by the sum and the carry bit at the end:

 0 + 0 = 0 | 0
 0 + 1 = 1 | 0
 0 + 2 = 2 | 0
...
15 + 13 = 28 | 15
15 + 14 = 29 | 14
15 + 15 = 30 | 15

I'm not very experienced with programming, but I know enough to at least get me this far. I think that this could be fun to learn. Any guidance or references to external instructions would be greatly appreciated. I would also appreciate any comments on what I have presented here that could help me write better Verilog code.

Thanks!

• user16324: Store the table in an array, and print out the array at the end of the simulation in the format you want.

Answer 1

You can use nested for loops for the body of your table, and another for loop for the header. To show numbers within a line (and avoid the newline character), use $write instead of $display. Use $display to end a line. Refer to IEEE Std 1800-2017, section 21.2.1 The display and write tasks.

integer i, j;
initial begin
 $write(" ");
 for (i=1; i <= 15; i = i+1) begin
 $write("__ ");
 end
 $display;
 for (i=1; i <= 15; i = i+1) begin
 A = i;
 $write("%d | ", A);
 for (j=1; j <= 15; j = j+1) begin
 B = j;
 CIN = 0;
 #5;
 $write("%d ", S);
 #5;
 end
 $display;
 end
end

Output:

 __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ 
 1 | 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 
 2 | 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 
 3 | 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 
 4 | 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 
 5 | 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 
 6 | 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 
 7 | 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 
 8 | 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 
 9 | 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 
10 | 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 
11 | 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 
12 | 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 
13 | 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 
14 | 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 
15 | 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 

---

I'll let you have the fun of printing the header numbers and a table for the carry output :)