Single-cycle MIPS processor in Verilog (multiplexor)

Question

I only recently started to understand in Verilog. But I have a task to create single-cycle 32bit MIPS processor. Instructions I want to implement are

add, and, addi, addu.qb, addu_s.qb, beq, jal, jr, lw, or, slt, sub, sw

The processor should look like this: enter image description here

enter image description here

I'm stuck with the implementation of the left block. As far as I understand this is a multiplexer that accepts 4 inputs and 3 selects(PCSrcJr, PCSrcJal, PCSrcBeq true). But I don't understand how to implement it. I can write a multiplexer with a single select.

module mux_4_1 ( input i1, i2, i3, i4, 
 input sel,
 output out
 );
reg out;
always @(sel or i1 or i2 or i3 or i4) begin
case (sel)
2'b00: out = i1;
2'b01: out = i2;
2'b10: out = i3;
2'b11: out = i4;
endcase
end
endmodule

• Mitu Raj: If you designed that block diagram, then you should be able to explain how that mux works as well. Is that a 3-bit select line, which makes it a 8:1 mux?
• soul_dp: Yes. As far as I understand all the selectors are single-bit and the inputs are 32-bit.
• Shashank V M: sel is declared as 1 bit wide, how can you use it as a 2-bit wide signal in your code?

Answer 1

As far as I can tell, the part you are looking at is a multiplexer without a decoder.

The decoder portion takes an \$n\$-bit number and converts it into a one-hot \2ドル^n\$ wide signal. Each of those bits in a typical multiplexer would select one of the possible data inputs.

In your case the decoder is part of the control unit, not the multiplexer. Which means your multiplexer needs to select the output based essentially on a priority basis (if you know the signals are one-hot, this simplifies the logic further).

• When PCSrcBeq is high, it will select the beq input
• When PCSrcJr is high, it selects the jr input
• When PCSrcJal is high it selects the jal input
• Otherwise if none of them are high, it selects the 0 input.

Answer 2

After executing an instruction the program counter PC is usually incremented by 4 (4 bytes or 32- bit). This is the default input 0 of the multiplexer.

However, if it is one of the conditional or unconditional branching instructions we do the following:

• if beq (branch if equal) we consider the 16-bit offset in the instruction code, we extend the sign ( to have a 32-bit address offset), we multiply it by 4 (<<2) to get it byte-addressed and we add it to PC+4.

• if jal (jump and link) we consider a specified offset in the

  instruction code to PC for unconditional branch.

• if jr (jump register) a register is assigned to PC also unconditional branch.