Simulation performance of bitwise operators and binary arithmetic Operators

Question

In terms of performance if you have say two inputs a and with the same bit width say 64. If you apply a bitwise operator and binary arithmetic operator (verilog/system verilog), which one takes longer to evaluate and why?

For example, in terms of a parity circuit when the parameters are change I observed a big difference in terms of simulation time while for an adder, the difference in simulation time isn't much. Code for adder and parity circuits are shown below.

module adder #(parameter width=64)(input logic [width-1 : 0] a, b, input cin, output logic cout, output logic [width-1:0] sum); 
 always @(a, b or carry_in) begin 
 {cout, sum} = a + b + cin;
 end 
 endmodule
module eparity #(parameter width=128)(input logic [width-1 : 0] data, output logic p); 
 logic [width : 0] i_parity; 
 genvar i; 
 assign i_parity[0] = 0; 
 for(i = 0; i < width; i = i + 1) begin 
 assign i_parity[i+1] = data[i] ^ i_parity[i]; 
 end 
 
 assign p = i_parity[width]; 
 endmodule

• Eugene Sh.: Look at the synthesized circuit and see the gates. Or run timing analysis. Each synthesizer can have different ways of implementing it.
• Light: Even for the same implementation tool, the constraint can affect the resulting netlist greatly. And the latest tools are clever enough to convert those fixed, simple arithmetic operation to bitwise operation.

Answer 1

The key difference in a bit wise operator is that the number of bits has no effect on performance—each bit operation is independent of the other bits. But once you get to arithmetic operators then there is a dependency from LSB to MSB that creates a long timing arc.

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Updated Answer to an almost entirely different question

What you are seeing is a difference in the level of coding abstraction. Simulators can add two 64 bit numbers on the host machine in one cycle. But if you wrote out the addition in terms of a sequence of Boolean equations, that would certainly take more simulation time. If you wrote the parity equation as

p = ^data;

That would certainly take less simulation time.

• user2987773: when I have an adder like this {c_o, sum} = a + b + c where a and b 64 bit and a parity circuit say parity = parity ^ data[i] where data = 128 bit. Testing these two circuits using icarus I observed the parity circuit takes longer.
• dave_59: There's a big difference between performance of the tools you're using versus performance of the design you're trying to implement. icarus is a simulation tool and you are at the mercy of how they coded and optimized a particular operation which might be different if you used another tool for the same source code. A lot of that depends on which language the tool was written in and how it generates code to simulate it.
• user2987773: I have updated the question, I think what I actually meant was when the parameter for an adder circuit is changed the simulation time isn't much. However, for a parity circuit the difference was quite huge. Was wondering why that might be the case. I have added sample codes to the question.