FPGA Timing Constrain Problem

Question

I am using the Cyclone V DE1-SoC in transferring data between HPS and FPGA, using 2 FIFO. I am facing a problem of very late data arriving time, causing the slack to be very negative.

...
if ((Processing_state == 4'd5) && (FPGA_to_HPS_state == 0))
 begin
 a <= a + memo[i] * memo[i];
 Processing_state <= 4'd4 ;
 end 
 
if (Processing_state == 4)
 begin
 
 if (|a == 0)
 begin
 k<=a;
 Processing_state <= 4'd0 ;
 end
 
 else if (|a != 0)
 begin
 
 if(j == 20479)
 begin
 b <= a >> 12 ;
 Processing_state <= 4'd4; //signal fpga the data is ready to be sent
 end
 
 else
 begin
 j <= j + 1;
 Processing_state <= 4'd0 ;
 end
 end
 end
 
 if (Processing_state == 4)
 begin
 Processing_state <= 3; 
 data_buffer_valid <= 1'b1 ;
 c <= b;
 
 end
 
 if (Processing_state == 3)
 begin
 Processing_state <= 2; 
 mean <= c / 5;
 end
 
 if (Processing_state == 2)
 begin
 Processing_state <= 1;
 meaninput <= mean;
 end
 
 if (Processing_state == 4'd1)
 begin
 Processing_state <= 4'd0 ; 
 data_buffer_valid <= 1'b1 ;
 a <= 0;
 j <= 0;
 
 end
...
if ((FPGA_to_HPS_state==0) && (!(fpga_to_hps_in_csr_readdata[0])) && data_buffer_valid)
 begin
 fpga_to_hps_in_writedata <= meaninput;
 fpga_to_hps_in_write <= 1'b1 ; //write flag
 FPGA_to_HPS_state <= 4'd1 ;
 end
...

The compile report is telling there is a problem on the line mean <= c / 5;

enter image description here

But the strange thing is when I change the line fpga_to_hps_in_writedata <= meaninput; to fpga_to_hps_in_writedata <= c; the problem disappear, the compile report about the timing didn't show the problem anymore.

fpga_to_hps_in_writedata will write the data of to the FIFO to send to HPS

Is this a problem on FIFO that something I need to change in Qsys? I've read the recommendation but I've only learned about basic Verilog so no idea about the timing constraint.

Answer 1

Integer division in combinatorial logic is very expensive in terms of both logic and time. You may want to find another way to get this result — perhaps there's a way to pipeline it, or use multiplication by 1/5.

• johnny2231: You are right, after some research I found that the division seems like is the problem. link. I am now learning how to write a division module instead of using the operator / to see if the problem can be solved or not.
• johnny2231: Hi Dave, do you mind if I ask again, I am having a square root module, originally it uses * operator to multiple, but I found that it is expensive too, so I modified it to <<, but I still got timing problem if I instantiate it to my FIFO, is it because I using the for loop? Because I need it to root 64 bits input, which needs to loop for 32 times. Is that might be the problem?
• Dave Tweed: Yes, combinatorial square root has a similar level of complexity as divide.
• johnny2231: Alright, thanks! Means the only way I can solve it is use clocked counter instead of for loop.