Quartus synthesises memory in logic despite verilog synthesis attribute

Question

I have the following read-only memory module:

import Signals::*;
module ProgramMemory(input logic [PC_SIZE:0] pc,
 output logic [IS:0] ir
);
 (* romstyle = "M10K" *) logic [IS:0] memory [MEM_SIZE:0];
 initial
 $readmemb("program.mem", memory);
 assign ir = memory[pc];
endmodule // ProgramMemory

When it is synthesized for a Cyclone V the ROM is implemented in logic rather than dedicated read-only memory. How can I make this work?

I've turned of the minimum ROM and RAM sizes in the project settings.

IS = 10, MEM_SIZE = 10

Answer 1

You've specified a completely asynchronous memory. AIUI, you can only use block RAM if the inputs (addresses) and/or outputs pass through pipeline registers — at least one or the other, but you'll get the best performance if you do both. The synthesis process can then map those pipeline registers to registers that are part of the block RAM structure on the chip.