How to assign a single output to different modules in Verilog?

Question

I have designed a simple ALU using Floating Point IP Cores in Xilinx ISE. I have an adder, a subtractor, and a multiplier. The IP Core of addition does the subtraction too and we have only two modules of addition and multiplication.

Inputs and outputs for each module is as following:

Inputs: a, b, clk, ce

Outputs: result, overflow, underflow, invalid_op, rdy

I want to connect the outputs of the modules to the outputs of the top module ALU (e.g [8:0] result of ALU to the result outputs of the two modules). How can I do this?

Here is the code:

module ALU( a, b, select, clock, 
 underflow, overflow, invalid_op, ready, result );
//inputs
input clock;
input [8:0] a;
input [8:0] b;
input [1:0] select;
//outputs
output underflow;
output overflow;
output invalid_op;
output ready;
output [8:0] result;
//registers
reg rdy;
reg [1:0] ce;
//wires
wire [8:0] b_input; 
//for subtraction it makes the second input negative.
assign b_input = {select[0],b[7:0]};
//choose which block to be used
always @(posedge clock)
begin
 case(select)
 2'b 00:
 ce <= 2'b 01;
 2'b 01:
 ce <= 2'b 01;
 2'b 10:
 ce <= 2'b 10;
 2'b 11:
 ce <= 2'b xx;
 default:
 ce <= 2'b xx;
 endcase
end
FPAdd add_or_subtract_ipcore (
 .a(a), // input [8 : 0] a
 .b(b_input), // input [8 : 0] b
 .clk(clock), // input clk
 .ce(ce[0]), // input ce
 .result(result), // output [8 : 0] result
 .underflow(underflow), // output underflow
 .overflow(overflow), // output overflow
 .invalid_op(invalid_op), // output invalid_op
 .rdy(ready) // output rdy
 );
FPMult multiply_ipcore (
 .a(a), // input [8 : 0] a
 .b(b), // input [8 : 0] b
 .clk(clock), // input clk
 .ce(ce[1]), // input ce
 .result(result), // output [8 : 0] result
 .underflow(underflow), // output underflow
 .overflow(overflow), // output overflow
 .invalid_op(invalid_op), // output invalid_op
 .rdy(ready) // output rdy
 ); 

endmodule

Answer 1

In general, when you need "multiplexer", think "case statement". You already have a case statement — so do your output assignment there, too.

You'll need to create a separate bus for the output of each of your IP cores — result_add, result_mult, etc.