Problem with my 8-to-3 line priority encoder using verilog gate level description

Question

I am attempting to build a working 8-to-3 line encoder using gate level description in verilog. Although, I have working models, in terms of successful compilation and simulation, the recurring issue seems to be that my circuits just do not seem to implement the encoding and thus the priority as they should do.

For instance, when D2 should be encoded as, 100, 101, 110 and 111, it is only being encoded as 100 and 101 and instead D3 is commencing its encoding at 110 and 111, instead of 1000. Please see waveform below: waveform of issue faced

This is starting to be a pain in the backside, because regardless of which implementation I use, the results are always the same.

Please also see an example of one such description below:

module prior_otb_enco(Y, D, V);
 output [2:0] Y;
 input [7:0] D;
 input V;
 wire D7_not, D6_not, D5_not, D4_not, D2_not;
 wire wa0, wa1, wa2, wa3, wa4;;
 //instanitate gates
 not g0 (D7_not, D[7]),
 g1 (D6_not, D[6]),
 g2 (D5_not, D[5]),
 g3 (D4_not, D[4]),
 g4 (D2_not, D[2]);
 and g5 (wa0, D6_not, D4_not, D[3]),
 g6 (wa1, D5_not, D4_not, D[3]),
 g7 (wa2, D5_not, D4_not, D[2]),
 g8 (wa3, D6_not, D[5]),
 g9 (wa4, D6_not, D4_not, D2_not, D[1]);
 or g11(Y[2], D[7], D[6], D[5], D[4]),
 g12(Y[1], D[7], D[6], wa1, wa2),
 g13(Y[0], D[7], wa0, wa3, wa4),
 g14(V, D[0], D[1], D[2], D[3], D[4], D[5], D[6], D[7]);
endmodule

Therefore, any insights that anyone can provide will be very much appreciated.

• user105652: Welcome to EE.SE. You might want to look at the diagram for a 74LS148. It is an 8 to 3 inverting priority encoder. Only the highest priority input set low is encoded and inverted, such that if input 0 is low the output is 0x07. Sometimes the hardware helps understand the logic needed in the software.
• aLoHa: Thanks @Sparky256. I was just in the midst of looking at the logic diagram for HCF4532B. But, I'll certainly get onto the 74LS148 diagram once I'm done with the HCF4532B one. Thanks again :)
• aLoHa: On a sidenote @Sparky256, is that your way of saying that one cannot always rely simply on the Boolean functions for correct implementation? :)
• The Photon: For one thing you have V as an input to your module, but then you also connect it to the output of g14.
• user105652: What I am pointing out is that the pure logic of hardware helps get past the abstraction of software. Once understood you can spot minor errors in your code that are "illogical" in terms of getting the function you want. The Photon may have already spotted a simple typo. The code has to be as perfect as the hardware version, but code has options hardware does not.

Answer 1

Just to summarize for you what I wrote in comments since it may help others, as well.

---

Here is the verilog I'd consider:

module prior_otb_enco( Y, D, V );
 output [2:0] Y;
 input [7:0] D;
 output V;
 wire s0, s1, s2, s3, s4, s5, s6, s7;
 wire Y2_temp;
 assign s0 = ~ D[7];
 assign s1 = ~ D[6];
 assign s3 = (D[6] | D[5] | D[4]);
 assign s2 = ~ (s1 & D[5]);
 assign s4 = (s3 | D[2] | ~ D[1]);
 assign s5 = ~ s3;
 assign Y2_temp = ~ (s0 & s1 & s2 & ~ D[4]);
 assign s6 = ~ (s5 & D[2]);
 assign s7 = ~ (s5 & D[3]);
 assign Y[1] = ~ (s0 & s1 & s6 & s7);
 assign Y[0] = ~ (s0 & s2 & s4 & s7);
 assign V = ~ (s6 & s4 & s7 & ~ (Y2_temp | D[0]));
 assign Y[2] = Y2_temp;
endmodule

---

The equivalent schematic is:

enter image description here

---

Here are three different behavioral models, all in verilog, that would achieve about the same thing after synthesis:

example 1

module prior_otb_enco_1( Y, D, V );
 output [2:0] Y;
 input [7:0] D;
 output V;
 reg V;
 reg [2:0] Y;
 always @(D)
 V = 1;
 if ( D[7] ) Y = 7;
 else if ( D[6] ) Y = 6;
 else if ( D[5] ) Y = 5;
 else if ( D[4] ) Y = 4;
 else if ( D[3] ) Y = 3;
 else if ( D[2] ) Y = 2;
 else if ( D[1] ) Y = 1;
 else if ( D[0] ) Y = 0;
 else
 begin
 V = 0;
 Y = 3'b X;
 end
 end
endmodule

example 2

module prior_otb_enco_2( Y, D, V );
 output [2:0] Y;
 input [7:0] D;
 output V;
 reg V;
 reg [2:0] Y;
 always @(D)
 begin
 V = 1;
 casex( D )
 8'b 1XXXXXXX: Y = 7;
 8'b 01XXXXXX: Y = 6;
 8'b 001XXXXX: Y = 5;
 8'b 0001XXXX: Y = 4;
 8'b 00001XXX: Y = 3;
 8'b 000001XX: Y = 2;
 8'b 0000001X: Y = 1;
 8'b 00000001: Y = 0;
 default:
 begin
 V = 0;
 Y = 3'b X;
 end
 endcase
 end
endmodule

example 3

module prior_otb_enco_2( Y, D, V );
 output [2:0] Y;
 input [7:0] D;
 output V;
 reg V;
 reg [2:0] Y;
 integer N;
 always @(D)
 begin
 V = 0;
 Y = 3'b X;
 for( N = 0; N < 8; N = N + 1 )
 if ( D[N] )
 begin
 V = 1;
 Y = N;
 end
 end
endmodule

• aLoHa: Hi there, I'm still learning my way around this site and was wondering how one obtains a score for a question posed? This question has been viewed over 2000 times, but has yet to obtain a singe score.
• jonk: @aLoHa I've never been asked that question before. I suppose you could ask, like you just did. I don't mind adding a +1. But, as best I understand it, one writes a question that is notable for its clarity in setting a context, shows substantial due diligence proving that everything that could be reasonably done has been done already, and asks just a single, well-focused question that is interesting and/or useful and can be directly answered without writing a book. Not a lot of questions here meet that test.
• aLoHa: Thank you very much for your prompt response, the insight and also the score for the question. I can imagine that it is not easy to come up with unique questions that meets all those criteria on here; but I'd like to think that the questions which I pose have a level of authenticity to them :)
• jonk: @aLoHa I usually work hard to communicate well when I'm answering. I expect to see similar efforts by questioners. It's not fair or respectful of the time of others to write questions which don't illustrate a similar effort to communicate as well as possible, I think. It's okay to not know things. I don't mind that. But I do mind if the questioner can't be bothered to put in substantial effort in framing the situation, communicating as well as possible, and allowing a direct answer rather than writing a book on some broad topic.
• jonk: @aLoHa Authenticity matters, of course. But that goes without saying. No one appreciates disingenuousness. So of course that is important, too. But it doesn't by itself make for a good question. It's just that the lack of it would make for a bad question, I think.