How can I design a 8 to 3 priority encoder using 4 to 2 priority encoders?

Question

This is what I've done so far and I really don't understand how to continue. The V variable is for verification

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[EDIT]

it works for Y2 and Y0, but it doesn't work for Y1 enter image description here

Answer 1

I'm not sure how to give you a hint without giving you the complete answer.

But consider the difference between these two situations:

• If any of the inputs to the upper encoder are asserted, then its outputs become the overall outputs, and Y2 needs to be asserted.
• If none of the inputs to the upper encoder are asserted, then the outputs of the lower encoder become the overall outputs, and Y2 needs to be negated.

Answer 2

Connect Y0, Y1 to both 4:2 in parallel. Use Y0 as the 3rd "address" line and a NOT gate to enable one or the other.

• Dave Tweed: Not sure where you're going with this. It's actually the V output of the upper encoder that becomes the third Y output. And you also need to mux the two V together to create the overall V output.
• CrossRoads: I see, so the desired result is turning say 1 only of I0 to I7 being High or Low into a 3-bit outcome?
• Dave Tweed: No, it's a priority encoder. Any combination of inputs can be asserted, and it's the topmost asserted input that gets encoded.
• CrossRoads: Ok. Never had to design that functionality into any design I've done.