Structure Identification in HDL codes

Question

I wanted to automatically Identify some structures in HDL code (Verilog/VHDL), let say an adder. I need to automatically detect how many adders in the design. I am not sure from where to start, should I like convert my code into AST (abstract syntax tree) look for pattern and then convert it back to Verilog/HDL ? can anyone mention an example or a small tutorial on how to do such tasks ? Thanks

• koalag: GHDL offers something that might be useful to you. I can't say anything about how useful it is, I only used it once.
• Sourabh Tapas: You can compile and check the rtl schematic of ur code. It will give you the digital blocks being implemented if that's what you meant by "structure"
• Paebbels: Identifying adders is more complicated then just creating an AST or similar structure. You need to synthesize the HDL description. This means translate HDL into a schematic. Then you can identify structures in the schematic like adders. Can't you parse synthesis log files? These contain messages like signal xyz was translated to an adder.

Answer 1

Use high-level synthesis software, even though electronic design automation (EDA) software for hardware construction languages (HCLs) may do the job better.

Using HCL models with HCL-supporting EDA software would involve creating new HCL models, or translating HDL models to HCL models.

HCLs include the following:

• Python-based HCLs:
  • PyMTL (from Cornell)
  • PyRTL (from UC Santa Barbara)
  • PyLog (from UIUC)
  • PyGears (from Serbia, now commercialized by a start-up)
  • MyHDL (from Europe)
• Scala-based HCL/HDL: Chisel HDL (from UC Berkeley), Spinal HDL (from Europe)
• OCaml-based HCL: Hardcaml, from Jane Street Capital
• Haskel-based HCL: Clash or C$\lambda$ash, from University of Twente

Picking up a HCL based on Python is doable, especially the more popular PyMTL.

Trying to do likewise with Clash, Hardcaml, or even Chisel HDL can be very challenging.

The emerging hot research trends, and commercial EDA trends, towards domain-specific computing, using high-level synthesis or some variant, or domain-specific compilers or deep neural network compilers, mean that more people will be using compiler design technology (especially for middle-end compiler frameworks/libraries/platforms, like LLVM) that intersects with program analysis and high-level synthesis. These middle-end compiler frameworks/libraries/platforms can also be used for microarchitecture research, and hardware security research.

Hence, you can find recently published work on high-level synthesis, or front-end variants of silicon compilation for HCLs, and you can probably find open-source implementations of high-level synthesis tools described in these research papers. There are papers regarding high-level synthesis dating back to the late 1980s. So, you can find old/older research publications about high-level synthesis, and their corresponding open-source high-level synthesis tools from academia.

When high-level synthesis tools parse behavioral models, or electronic system-level models, into the 2-tuple of control flow graph (CFG) and dataflow graph (DFG), or the hybrid control/data flow graph (CDFG), the DFG/CDFG will represent dataflow operations associated with addition, multiplication, or matrix operations with operators in the DFG/CDFG.

By counting the number of addition operators in the optimized DFG/CDFG, you can determine the number of adders needed for their logic circuit representation of the CDFG, or DFG + CFG.

You can add a trace statement to print the number of addition operators in the optimized DFG/CDFG, and subsequently the number of adders needed for their logic circuit representation of the CDFG (or DFG + CFG).

Or, you can roll your own DFG/CDFG circuit analysis (analogous to program analysis for HCLs and modern HDLs) with LLVM/FIRRTL/CIRCT.