Default assignment in VHDL

Question

I'm a little confuse about this default assignment concept. Normally, in order to avoid a latch, we should explicitly give a value to a signal in every case. For example:

-- Assuming a is std_ulogic and b is std_ulogic_vector(3 downto 0)
process(a, b)
begin
 if a = '1' then
 b <= "1010";
 else
 b <= "0101";
 end if;
end process;

But why in the following process, an else statement is not necessary.

process(clock, reset)
begin
 if reset = '1' then
 b <= "0000";
 elsif rising_edge(clock) then
 b <= b_next;
-- Why don't we need an else statement here?
 end if;
end process;

Can anyone help me out? Thanks!

Answer 1

Within your target device, be it FPGA, CPLD, ASIC or PLA, the configurable digital logic is implemented (a) by combinatorial gates or (b) by registers (latches or flip-flops).

Combinatorial logic implements AND, OR, XOR and NOT functions and their derivatives, like mux, NAND, NOR and so on. A combinatorial logic circuit can transform its input pattern to a new output pattern. A combinatorial logic circuit always produces one repeatable output for each combination of its inputs.

A register is a 1-bit memory. It can simply copy its data input to its data output in response to an edge (flip-flop) or level (latch) on its clock input. Registers can also have asynchronous set and reset inputs that change the output without clock changing.

In VHDL, you describe (model) the behaviour you would like and the synthesis software tool tries to make a circuit to do it using the configurable digital logic in your target device. Your VHDL implies the circuit behaviour it wants. The synthesis tool attempts to infer these functions from your VHDL and produce the desired logic circuit.

In your VHDL, combinatorial functions must be implied by concurrent statements or by a process that always produces an output for every combination of its inputs. Registers must be implied by a process that only changes in response to (a) a level or edge event on a single input representing the register clock and (b) one input representing set/reset that loads 1's or 0's (but not other signals) into the output signals.

If your VHDL contains a process that is intended to be combinatorial but does not produce an output for every pattern on its inputs, it will infer that a latch is required because at least one output is being shown to stay the same.

So in your examples, the process you question is implying a D-type Flip-Flop (DFF). Under the conditions that reset is inactive and the clock has not risen, the digital logic register output must stay the same. Accordingly, this process must not contain an 'else' term describing what to do when reset is inactive and clock has not risen.