VHDL Assignment Statement

Question

In my ASIC book they are developing a state machine, and they have a statement like:

 Shift <= '1' when State = S else '0'; 

However in my project I have multiple states that have the same output being required to turn on so is it possible to write VHDL like this:

 Shift <= '1' when State = S OR State = E OR STATE = Q else '0'; 

Or do I have to assign Shift for each of my states?

Answer 1

Yes that is doable

Shift <= '1' when ((State = S) OR (State = E) OR (STATE = Q))
 else '0'; 

• user16324: The parentheses are unnecessary; the code in the question was already correct.
• alexan_e: @BrianDrummond I think it's a good habit to parenthesize conditions in any "programming" language, it makes things much clearer.
• Martin Thompson: @alexan_e: although some take the view that excessive parens are less clear... I would certainly remove the outer parens