I am working on coding a Regsiter a1
with input signals b1,rst
and wra1
the register a1
is initialized to a specific value at reset.
a1
only changes its value to b1
when wra1
is 1
else it keeps the old value
process(clk,regrst)
begin
if(regrst='1')then
a1 <= (others =>'0');
elsif(clk'event and clk='1') then
if(wra1='1')then
a1 <= b1;
end if;
end if;
end process;
In this statement I have written the register process to update on the needed wra1 signal but I am confused on how to make it keep the old value of the output in case this write signal is 0 does this concept generate unintended latches to store the previous value? if so what can I add as a default register assignment in the begning of the process ? and should I include the else statement with
a1<=a1;
Thank you
-
1\$\begingroup\$ Your code generates a register with asynchronous reset and write enable as intended. A else statement is not needed. This works because your sensitivity list has only asynchronous signals listed (the clock and reset signal). Unless there is a rising edge, there can't be any changes except for reset. So this is a true flip flop behavior, not a latch behavior :) \$\endgroup\$Paebbels– Paebbels2014年12月20日 13:51:24 +00:00Commented Dec 20, 2014 at 13:51
1 Answer 1
As Paebbels mentions in his comment, your process works exactly as you intend it.
You get a flip-flop, and not a latch, because of the condition on clk
in your if statement, which specifies that a1
is assigned only when clk rises. clk'event
means a change just happened on clk
, so clk'event and clk='1'
means "clk
just changed and is now one", i.e. a rising edge.
A default assignment as the one you propose is not necessary because a signal keeps its previous value if one is not assigned explicitly. This simplifies sequential processes as the one you posted, but is also the source of unwanted latches in combinatorial processes.
The following is a latch:
process(wra1, b1) begin
if(wra1='1')then
a1 <= b1;
end if;
end process;
Note that 1) this process has no clock (i.e. no rising edge condition on a signal), just like a process describing combinatorial logic, but 2) no value is assigned to a1
when wra1
is not 1, which means it keep its current value until wra1
is 1 again, even if b1
changes. That's the semantic of a latch.