Test in VHDL of working frequency of a combinatorial component

Question

I want to measure approximately working frequency of a combinatorial component. To do this, I use a my implementation of scan-chain to wrap my ripple carry adder. This is my code:

--Ripple carry wrapped using scan chain
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ripple_carry_clocked_m is
 generic (size : integer:=8);
 Port ( data_in : in STD_LOGIC;
 clock : in STD_LOGIC;
 data_out : out STD_LOGIC
 );
end ripple_carry_clocked_m;
architecture Structural of ripple_carry_clocked_m is
component ripple_carry_m is
 generic (size : integer:=8);
 Port ( a : in STD_LOGIC_VECTOR (size-1 downto 0);
 b : in STD_LOGIC_VECTOR (size-1 downto 0);
 cin : in STD_LOGIC;
 overflow : out STD_LOGIC;
 sum : out STD_LOGIC_VECTOR (size-1 downto 0));
end component;
component scan_chain_m is
 generic(N : natural:=8; 
 right_left_n : bit:='1'); 
 Port ( D : in STD_LOGIC_VECTOR(N-1 downto 0);
 SI : in STD_LOGIC; 
 SE : in STD_LOGIC; 
 clk : in STD_LOGIC; 
 clear_n : in STD_LOGIC;
 enable : in STD_LOGIC; 
 SO : out STD_LOGIC; 
 reg_out : out STD_LOGIC_VECTOR(N-1 downto 0) 
 );
end component ;
signal s_sum: std_logic_vector (size-1 downto 0):= (others=>'0');
signal s_overflow: std_logic:= '0';
signal s_data: std_logic_vector (2*size downto 0):= (others=>'0');
begin
 IST_SCAN_CHAIN1 : scan_chain_m generic map(2*size+1,'1') port map(
 SI => data_in,
 D => (others=>'1'),
 SE => '1',
 enable => '1',
 clear_n => '1',
 clk => clock,
 SO =>open,
 reg_out => s_data);
 IST_RIPPLE_CARRY: ripple_carry_m generic map(size) port map(
 a => s_data(2*size downto size+1),
 b => s_data(size downto 1),
 cin => s_data(0),
 overflow => s_overflow,
 sum => s_sum);
 IST_SCAN_CHAIN2 : scan_chain_m generic map(size+1,'1') port map(
 SI => '0',
 D => s_overflow & s_sum,
 SE => '1',
 enable => '1',
 clear_n => '1',
 clk => clock,
 SO =>data_out,
 reg_out => open);
end Structural;

Scan chain code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity scan_chain_m is
 generic(N : natural:=8; -- lenght register
 right_left_n : bit:='0'); -- right shift = 1, left shift =0
 Port ( D : in STD_LOGIC_VECTOR(N-1 downto 0); 
 SI : in STD_LOGIC; -- bit in shifted
 SE : in STD_LOGIC; --SE=0 register, SE=1 shift register
 clk : in STD_LOGIC; --frequenza di lavoro
 clear_n : in STD_LOGIC; --reset register
 enable : in STD_LOGIC; 
 SO : out STD_LOGIC; --bit out shifted
 reg_out : out STD_LOGIC_VECTOR(N-1 downto 0) 
 );
end scan_chain_m ;
architecture Structural of scan_chain_m is
component flop_m is
 Port ( D : in STD_LOGIC; 
 SI : in STD_LOGIC; 
 SE : in STD_LOGIC; 
 clk : in STD_LOGIC;
 clear_n : in STD_LOGIC;
 enable : in STD_LOGIC;
 Q : out STD_LOGIC); 
end component;
signal sq : std_logic_vector(N-1 downto 0):=(others=>'0');
begin
 RIGHT_SHIFT : if(right_left_n='1') generate
 CHAIN_RIGHT : for k in N-2 downto 0 generate
 IST_K_RIGHT : flop_m port map(
 D => D(k),
 SI => sq(k+1),
 SE => SE,
 clk => clk,
 clear_n => clear_n,
 enable => enable,
 Q => sq(k));
 end generate CHAIN_RIGHT; 
 IST_IN_RIGHT : flop_m port map(
 D => D(N-1),
 SI => SI,
 SE => SE,
 clk => clk,
 clear_n => clear_n,
 enable => enable,
 Q => sq(N-1));
 SO <= sq(0);
 reg_out <= sq;
 end generate RIGHT_SHIFT;
 LEFT_SHIFT : if(right_left_n='0')generate
 CHAIN_LEFT : for k in 1 to N-1 generate
 IST_K_LEFT : flop_m port map(
 D => D(k),
 SI => sq(k-1),
 SE => SE,
 clk => clk,
 clear_n => clear_n,
 enable => enable,
 Q => sq(k));
 end generate CHAIN_LEFT;
 IST_IN_LEFT : flop_m port map(
 D => D(0),
 SI => SI,
 SE => SE,
 clk => clk,
 clear_n => clear_n,
 enable => enable,
 Q => sq(0));
 SO <= sq(N-1);
 reg_out <= sq;
 end generate LEFT_SHIFT;
end Structural;

Controlled flip-flop code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity flop_m is
 Port ( D : in STD_LOGIC; 
 SI : in STD_LOGIC; 
 SE : in STD_LOGIC; 
 clk : in STD_LOGIC; 
 clear_n : in STD_LOGIC; 
 enable : in STD_LOGIC; 
 Q : out STD_LOGIC); 
end flop_m;
architecture Structural of flop_m is
component flip_flopD_m is
 Port ( D : in STD_LOGIC;
 reset_n : in STD_LOGIC;
 preset_n : in STD_LOGIC;
 enable : in STD_LOGIC;
 clk : in STD_LOGIC;
 Q : out STD_LOGIC);
end component;
component mux2_1_m is
 port (a,b,sel : in std_logic;
 y : out std_logic);
end component;
signal mux_d : std_logic; --uscita del multiplexer
begin
 mux2_1 : mux2_1_m port map(
 a => D,
 b => SI,
 sel => SE,
 y => mux_d);
 mem_cell: flip_flopD_m port map(
 D => mux_d,
 reset_n => clear_n,
 preset_n => '1',
 clk => clk,
 enable => enable,
 Q => Q);
end Structural;

Omit flip flop, multiplexer and RCA codes for simplicity

When I synthesize(using Xilinx tool ISE), it gives me back this warning:

WARNING:HDLCompiler:946 - "ripple_carry_clocked_m.vhd" Line 84: Actual for formal port d is neither a static name nor a globally static expression
WARNING:Xst:1290 - Hierarchical block <IST_SCAN_CHAIN1> is unconnected in block <ripple_carry_clocked_m>. It will be removed from the design.
WARNING:Xst:1290 - Hierarchical block <IST_RIPPLE_CARRY> is unconnected in block <ripple_carry_clocked_m>.It will be removed from the design.

I don't understand where I forget the connections. Can you help me please?

• user16324: You might want to tell us which "line 84" gives the error. But apparently you're connecting something that isn't either a static name or a static expression (like '1') to a port, and while it may or may not be legal VHDL, it's something ISE has trouble with, so best better avoided. If it's the line D => s_overflow & s_sum, create an intermediate signal, assign that expression to it' and connect that to the port.
• alukard990: @BrianDrummond line 84 is that you said. I add an intermediate signal s_rc_out <= s_sum & s_overflow but warning that indicate connectionless there are still
• alukard990: No one can help me?

Answer 1

Continuing from @BrianDrummond's approach, I am not sure if ISE supports this statement:

D => (others=>'1')

could you try replacing this with a signal that's been assigned the same value and try.

My rationale of looking at the very first block is that if it's output is not being used, the downstream logic doesn't matter.

• alukard990: ISE support that assignment

Answer 2

My solution in Xilinx forum https://forums.xilinx.com/t5/Synthesis/Test-in-VHDL-of-working-frequency-of-a-combinatorial-component/td-p/734768. It works!