AND gate between 2 std_logic_vector Isn't working correctly

Question

I am trying to do a multiplication between 2 std_logic_vector have the following testbech:

LIBRARY ieee;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_arith.ALL;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
ENTITY mult_tb IS
END mult_tb;
ARCHITECTURE behavior OF mult_tb IS 
 -- Component Declaration for the Unit Under Test (UUT)
 COMPONENT Full_vector_multiplier
 PORT(
 ma : IN std_logic_vector(23 downto 0);
 mb : IN std_logic_vector(23 downto 0);
 mr : OUT std_logic_vector(47 downto 0)
 );
 END COMPONENT;
 --Inputs
 signal ma_tb : std_logic_vector(23 downto 0) := "000000000000000000001111";
 signal mb_tb : std_logic_vector(23 downto 0) := "000000000000000000000111";
 signal mr_tb : std_logic_vector(47 downto 0) ;
 signal u : std_logic_vector(47 downto 0) := (others => '0');
BEGIN
 u<=ma_tb*mb_tb;
 -- Instantiate the Unit Under Test (UUT)
 uut: Full_vector_multiplier PORT MAP (
 ma => ma_tb,
 mb => mb_tb,
 mr => mr_tb
 );
 -- Stimulus process
 process
 begin 
 wait;
 end process;
END;

For testing this multiplication module:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Full_vector_multiplier is
 generic(msb2 : integer:=23);
 port(
 ma : in std_logic_vector(msb2 downto 0);
 mb : in std_logic_vector(msb2 downto 0);
 mr : out std_logic_vector(msb2*2+1 downto 0)
 );
end Full_vector_multiplier;
architecture Behavioral of Full_vector_multiplier is
COMPONENT full_vector_adder
 generic(msb : integer:=47
 );
 PORT(
 i1 : IN std_logic_vector(msb downto 0);
 i2 : IN std_logic_vector(msb downto 0);
 s : OUT std_logic_vector(msb downto 0);
 c_out : OUT std_logic
 );
 END COMPONENT;
type minimatrix is array(0 to msb2) of std_logic_vector(msb2 downto 0);
type matrix is array(0 to msb2) of std_logic_vector(msb2*2+1 downto 0);
signal x : matrix:=(others=>(others=>'0'));
signal bt : matrix:=(others=>(others=>'0')); 
signal b1 : minimatrix:=(others=>(others=>'0'));
signal s_c_out : std_logic_vector(msb2 downto 0):=(others=>'0');
begin
mr<=x(x'right);
main : for i in 0 to msb2 generate
 b1(i)(i)<=mb(i);
 bt(i)(msb2+i downto i)<=b1(i) and ma;--line-A
 it0 : if i=0 generate
 x(i)<=bt(i);
 end generate it0;
 itothers : if i>0 generate
 addi : full_vector_adder port map(
 i1=>bt(i),
 i2=>x(i-1),
 s=>x(i),
 c_out=>s_c_out(i)
 );
 end generate itothers;
end generate main;
end Behavioral;

The problem is that I am trying to save or copy the vector ma in the bt array, shited i zeros in each generation of the main loop (line-A), and it(bt) seems to be only a ones diagonal: testbench: bt array

the b1 array is successfully filled with \$mb_i\$ in the \$b1_{ii}\$ "position": b1 in testbench

So, the question is if what I am doing wrong? It's only "line-A" the problem? because I need that bt be like:
|0.....ma|
|0...ma 0|
|0..ma 00| Thanks in advance.

Answer 1

in vhdl two distinct types of instruction could be used : sequential an concurrent. You can have a look at the difference between the two instructions have a look at the answer here . in your case you are using a concurrent statement generate which translates into the following :

 b1(i)(i)<=mb(i);
-- b1(0)(0)<=mb(0)
-- b1(1)(1)<=mb(1)
-- b1(2)(2)<=mb(2)
-- ..........
-- b1(23)(23)<=mb(23)
bt(i)(msb2+i downto i)<=b1(i) and ma; --line-A
-- bt(0)(23 downto 0)<=b1(0) and ma;
-- bt(1)(24 downto 1)<=b1(1) and ma;
-- bt(2)(25 downto 2)<=b1(2) and ma;

analyzing that you can see that, since you initialized your signals here :

signal bt : matrix:=(others=>(others=>'0')); 
signal b1 : minimatrix:=(others=>(others=>'0'));

they all start with zeros. In the expansion of your concurrent code b1(i)(i)<=mb(i); as you can see from my comments above, you are constantly assigning the b1(i)(i) to one single bit of the mb and the rest is filled with zeros. you are then moving the whole vector of b1(i) padding it with zeros on the left and right depending on its position. This is explains what you are seeing in the simulation. In order to achieve what you are asking for

|0.....ma| |0...ma 0| |0..ma 00|

you can simply avoid the first copy and the AND so that line-A becomes bt(i)(msb2+i downto i)<= ma; --line-A and as you can see b1 is not needed

• ego2509: Reading you answer I've found the whole problem, as you mentioned before, is that b1 is filled with zeros, so the and between those 2 vectors will always be just a bit length. Thank you so much, I solved my issue using another for generate filling those extra zeros.