Combinatorial loop of SR latch

Question

I implemented an SR latch in Verilog.

module sr_latch(
 output Q,
 output P,
 input S,
 input R
);
nor(P, S, Q);
nor(Q, R, P);
endmodule

However, Xilinx ISE reports a warning:

WARNING:Xst:2170 - Unit sr_latch : the following signal(s) form a combinatorial loop: n0000.

Is this warning avoidable for implementing an SR latch?

Should I just ignore it?

• Mitu Raj: No you can't. FPGAs are not meant for implementing latches in RTL. They have to be properly timed due to the combi feedback, which FPGA timing analysers can't do.

Answer 1

It doesn't seem avoidable. Even in this document by Xilinx themselves they use this Verilog code to generate an SR-latch

module SR_latch_gate (input R, input S, output Q, output Qbar);
 nor (Q, R, Qbar);
 nor (Qbar, S, Q);
endmodule
module SR_latch_dataflow (input R, input S, output Q, output Qbar);
 assign #2 Q_i = Q;
 assign #2 Qbar_i = Qbar;
 assign #2 Q = ~ (R | Qbar);
 assign #2 Qbar = ~ (S | Q);
endmodule 

which returns this warning when synthesizing (I couldn't recreate the warning you show in your question)

Critical Warning: 1 LUT cells form a combinatorial loop. This can create a race condition. Timing analysis may not be accurate. The preferred resolution is to modify the design to remove combinatorial logic loops.