hexadecimal seven segment display verilog

Question

I have a 4 bit output number as output. How can it be seen on seven segment display as hexadecimal number? I'm new and mentioning verilog.

case example:

wire [3:0] num;
case (num)
 4'b0000 : 1111110;
 4'b0001 : 0110000;
 4'b0010 : 1101101;
 4'b0011 : 1111001;
 so on
 .
 .
 4'b1111 : 1000111;
endcase

enter image description here

4 bit binary to seven segment

#TABLE: x1,x2,x3,x4 => a,b,c,d,e,f,g
0000 => 1111110
0001 => 0110000
0010 => 1101101
0011 => 1111001
0100 => 0110011
0101 => 1011011
0110 => 1011111
0111 => 1110000
1000 => 1111111
1001 => 1111011
1010 => 1110111
1011 => 0011111
1100 => 1001110
1101 => 0111101
1110 => 1001111
1111 => 1000111

• The Photon: That's basically it. In verilog you just write a big case statement. In an FPGA it isn't really any more costly than any other way of doing it because 1) FPGA logic is done with look-up tables anyway and 2) If the number of inputs can be reduced for one or the other of the segments, your synthesis tool should take care of that optimization.
• Hax: would you mind brightening some more? I've completely finished my multiplexer parts. Just I need to show them on seven segment display. I see case but what should I do? @ThePhoton
• The Photon: Have you looked up how to write a case statement in Verilog? What part don't you understand? Please edit your question to clarify what you need help with. Please don't just open up a new question asking the same thing over again.
• user16324: In VHDL you can use the CASE but it's simpler to declare a constant array (Lookup table) and index it using the 4-bit number. The same must be possible in Verilog, surely?
• Hax: I've edited the post. Is it right? Could you share your advises @ThePhoton

Answer 1

You need to assign the output value to some wire or register and then connect that net to an output pin.

Typical code (not tested) is

wire [3:0] num;
reg [6:0] out;
always @num begin
 case (num):
 4'b0000 : out <= 1111110;
 4'b0001 : out <= 0110000;
 4'b0010 : out <= 1101101;
 4'b0011 : out <= 1111001;
 // ...
 endcase
end

Declaring out as a reg type doesn't actually make it into a register or generate a flip-flop. It just allows you to assign to out inside an always block.

• Hax: If I have four fourbit number, should I write four always case? like always @num1 begin case (num1):always @num2 begin case (num2):always @num3 begin case (num3):always @num4 begin case (num4):
• B Pete: I think the OP is asking what to do if he has four hex digits. In that case, Instead of cutting and pasting four copies of the always block, it would be best to create a hex to seven segment module and instantiate it four times.