Difference between >> and >>> in verilog?

Question

What is the difference between >> and >>> in verilog/system verilog? I know that == tests for only 1 and 0, while === tests for 1, 0, X, Z. So how is that similar to the shift operator?

Answer 1

It is not similar to ==/===, if the left hand operand is signed then >>> performs sign extension.

reg signed [9:0] b = 10'sb11_0101_0101;
reg signed [9:0] a_signed;
reg [9:0] a_unsigned; 
always_comb begin
 a_signed = b >>> 2;
 a_unsigned = b >> 2;
end

Result:

#a_signed 1111010101
#a_unsigned 0011010101

Example on EDA Playground.

• Colin D Bennett: Wow, that is exactly the opposite of the meanings of the Java >> and >>> operators... wicked.
• dave_59: Verilog was 10 years before Java. :P
• The Photon: @dave_59, but signed values (aside from the 32-bit integer type) and the arithmetic shift operators were only introduced to Verilog in Verilog-2001.
• dave_59: Verilog already had >> to mean logical shift in 1985 (taken from Pascal, which is from 1970). So it had to use >>> for arithmetic shift.

Answer 2

According to IEEE1800-2012 >> is a binary logical shift, while >>> is a binary arithmetic shift.

Basically, arithmetic shift uses context to determine the fill bits, so:

• arithmetic right shift (>>>) - shift right specified number of bits, fill with value of sign bit if expression is signed, otherwise fill with zero,
• arithmetic left shift (<<<) - shift left specified number of bits, fill with zero.

On the other hand, logical shift (<<, >>) always fill the vacated bit positions with zeroes.

For example:

a = 5'b10100;
b = a <<< 2; //b == 5'b10000
c = a >>> 2; //c == 5'b11101, 'cause sign bit was `1`
d = a << 2; //d == 5'b10000
e = a >> 2; //e == 5'b00101

• Clément: The results of this example depend on the declaration of c: if you use reg [4:0] c, you'll get 5'b00101, not 5'b11101. Updating the example to clarify the types would be useful, I think.

Answer 3

Note: In logical shift (>> or <<) if number is signed or unsigned always insert zero at palace of vacant bits.

In arithmetic shift (>>> or <<<)

if number is signed then (in case >>>) MSB will be insert at palace of vacant bits, and (in case <<<) zero will insert at palace of vacant bits.

if number is unsigned then zero at palace of vacant bits.

Here Example:

input [4:0] a;

input signed [4:0] b;

output [4:0] c;

output signed [4:0] d;

if

assign c = a >> 2;

assign d = b >> 2;

then

0, inputs a=00100, b=01110,output c=00001, d=00011

10, inputs a=00001, b=01101,output c=00000, d=00011

20, inputs a=01001, b=11101,output c=00010, d=00111

30, inputs a=10101, b=10001,output c=00101, d=00100

40, inputs a=10001, b=10111,output c=00100, d=00101

if

assign c = a >>> 2;

assign d = b >>> 2;

then

0, inputs a=00100, b=01110,output c=00001, d=00011

10, inputs a=00001, b=01101,output c=00000, d=00011

20, inputs a=01001, b=11101,output c=00010, d=11111

30, inputs a=10101, b=10001,output c=00101, d=11100

40, inputs a=10001, b=10111,output c=00100, d=11101

if

assign c = a >>> 2;

assign d = b <<< 2;

then

0, inputs a=00100, b=01110,output c=00001, d=11000

10, inputs a=00001, b=01101,output c=00000, d=10100

20, inputs a=01001, b=11101,output c=00010, d=10100

30, inputs a=10101, b=10001,output c=00101, d=00100

40, inputs a=10001, b=10111,output c=00100, d=11100