Instantiating Parameterized Modules in SystemVerilog

Question

In SystemVerilog I would love to instantiate modules like

const int primeArray [11] = '{3, 5, 7, 11, 13, 17, 19, 23, 29, 31, 37};
logic clock, reset, increment;
logic [10:0] match;
generate
 genvar n;
 for (n = 0; n < 11; n++)
 begin
 PrimeCounter #(primeArray[n]) counter (.clock, .reset, .increment, .match(match[n]));
 end
endgenerate

Unfortunately primeArray[n] cannot be passed as a parameter, since apparently it is not truly constant. Is there a way to accomplish this? Or am I stuck instantiating

PrimeCounter #(3) counter0(.clock, .reset, .increment, .match(match[0]));
PrimeCounter #(5) counter1(.clock, .reset, .increment, .match(match[1]));
PrimeCounter #(7) counter2(.clock, .reset, .increment, .match(match[2]));
PrimeCounter #(11) counter3(.clock, .reset, .increment, .match(match[3]));
PrimeCounter #(13) counter4(.clock, .reset, .increment, .match(match[4]));
PrimeCounter #(17) counter5(.clock, .reset, .increment, .match(match[5]));
PrimeCounter #(19) counter6(.clock, .reset, .increment, .match(match[6]));
PrimeCounter #(23) counter7(.clock, .reset, .increment, .match(match[7]));
PrimeCounter #(29) counter8(.clock, .reset, .increment, .match(match[8]));
PrimeCounter #(31) counter9(.clock, .reset, .increment, .match(match[9]));
PrimeCounter #(37) counter10(.clock, .reset, .increment, .match(match[10]));

?

Answer 1

change const to parameter

parameter int primeArray [11] = '{3, 5, 7, 11, 13, 17, 19, 23, 29, 31, 37};
...
genvar n;
for (n = 0; n < 11; n++) begin : gen_loop
 PrimeCounter #(primeArray[n]) counter ( .match(match[n]), .* );
end

working example here

I added initial $display("%m id:%0d",id); into my PrimeCounter, output is as follows:

# dut.gen_loop[0].counter id:3
# dut.gen_loop[1].counter id:5
# dut.gen_loop[2].counter id:7
# dut.gen_loop[3].counter id:11
# dut.gen_loop[4].counter id:13
# dut.gen_loop[5].counter id:17
# dut.gen_loop[6].counter id:19
# dut.gen_loop[7].counter id:23
# dut.gen_loop[8].counter id:29
# dut.gen_loop[9].counter id:31
# dut.gen_loop[10].counter id:37