VHDL top module problems

Question

I have this top module

entity top is
Port 
 ( 
 CLock : in STD_LOGIC;
 LED : out STD_LOGIC_vector(3 downto 0);
 taster : in std_logic_vector(3 downto 0);
 teste_led: out std_logic;
 i_led: out std_logic_vector (2 downto 0)
 );
end top;
architecture Behavioral of top is
component game
port ( 
 LED1 : out STD_LOGIC_VECTOR (3 downto 0);
 CLK : in STD_LOGIC;
 winLed: out std_logic;
 switch: in std_logic_vector(3 downto 0);
 pointerLED: out std_logic_vector(2 downto 0) 
 );
end component;
begin
game1: game port map(LED1 => LED, CLK => Clock, winLed => teste_led, Switch => taster , pointerLed => i_led);
end Behavioral;

which i cannot see why isn't working. I've tested the game module by it self, and it work as it should be, but when i add it to this top module, nothing happens on my FPGA, eventhoug i am not getting any errors or warning?? what Am i doing wrong.

NET "switch" LOC = "G18";
 NET "taster<3>" LOC = "K17";
 NET "taster<2>" LOC = "K18";
 NET "taster<1>" LOC = "H18";
 NET "taster<0>" LOC = "G18";
 NET "teste_led" LOC = "R4";
 NET "i_led<2>" LOC = "F4";
 NET "i_led<1>" LOC = "P15";
 NET "i_led<0>" LOC = "E17";
 NET "LED<3>" LOC = "K14";
 NET "LED<2>" LOC = "K15";
 NET "LED<1>" LOC = "J15";
 NET "LED<0>" LOC = "J14";
 NET "CLock" LOC = "B8"; 

I did it exactly like this http://www.eng.auburn.edu/~strouce/class/elec4200/vhdhier.pdf I am therefore very confused on what i've done wrong.. Complete code: https://www.dropbox.com/s/mro1wmk2bjkigp1/randomnumber.rar

• stanri: Could you post your ucf file please?
• Carlton Banks: top port ucf added
• stanri: what is your clock frequency and is that your entire ucf?
• Carlton Banks: that is my entire .ucf for my top module. 50 Mhz
• stanri: Is there some other way I can see all the build report files? That link requires their downloader app. Dropbox, perhaps?

Answer 1

As far as I can see, your code looks fine. It's difficult to say what the problem is without seeing the build report files.

The Xilinx tools need to be told what the clock frequency of your clock is. This can be done by modifying your clock constraint as follows:

NET "CLock" LOC = "B8" | PERIOD = 50 MHz;

It's possible that the first time you were just lucky that the router met timing spec, and the second time round it didn't.