VHDL- counter problems

Question

I am trying to make an up/down counter on a Basys board. But I have some issues I can't figure out.

My code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity counter is
 Port (
 clock : in STD_LOGIC;
 clock_osc : in STD_LOGIC;
 reset : in STD_LOGIC;
 count_start : in STD_LOGIC;
 count_out : out STD_LOGIC_VECTOR (3 downto 0);
 AN1 : out STD_LOGIC;
 AN2 : out STD_LOGIC;
 AN3 : out STD_LOGIC;
 AN4 : out STD_LOGIC
 );
end counter;
architecture Behavioral of counter is
 signal count : std_logic_vector (3 downto 0);
 signal count2 : std_logic_vector (3 downto 0);
begin
 countupdown: process (clock, reset, count_start)
 begin
 if (reset = '0') then
 count <= "0000";
 count2 <= "0000";
 elsif (clock='1' and clock'event) then
 if (count_start = '0') then
 count <= count + 1;
 else 
 count2 <= count2 - 1;
 end if;
 end if;
 end process;
 count_out<= count when (clock_osc = '1') else count2;
 AN1<='0' when (clock_osc='1') else '1';
 AN2<='0' when (clock_osc='1') else '1';
 AN3<='1' when (clock_osc='1') else '0';
 AN4<='1' when (clock_osc='1') else '0' ;
end Behavioral;

The errors:

ERROR:HDLParsers:808 - "C:/Users/sana4/Desktop/uni/Digital Design/Counter3/counter.vhd" Line 75. + can not have such operands in this context.
ERROR:HDLParsers:808 - "C:/Users/sana4/Desktop/uni/Digital Design/Counter3/counter.vhd" Line 79. - can not have such operands in this context.

• Joe Hass: Please format your code properly, eliminate the extra blank lines, and tell us which lines are line 75 and 79.

Answer 1

I've taken the liberty of cleaning up your listing and formatting it for compactness and readability, so I've undoubtedly messed up the line numbering.

The specific errors you're getting are caused by the fact that you can't do arithmetic on std_logic_vector, e.g., to increment and decrement your counters. At a minimum, you need to include the library ieee.numeric_std in order to allow this. See the answers to this question for additional details.