VHDL: code warning problems

Question

I am having some problems with my code, and understandning what my warnings are trying to say to me..

These are the warnings i get

WARNING:Xst:737 - Found 4-bit latch for signal <counter_10>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 4-bit latch for signal <counter_1>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <ret>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:2677 - Node <Sreg_FSM_FFd1> of sequential type is unconnected in block <game>.
WARNING:Xst:2677 - Node <Sreg3_FSM_FFd1> of sequential type is unconnected in block <game>.
WARNING:Xst:2677 - Node <Sreg2_FSM_FFd1> of sequential type is unconnected in block <game>.
WARNING:Xst:2677 - Node <Sreg1_FSM_FFd1> of sequential type is unconnected in block <game>.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
 segment2/counter_1_cmp_eq0000 is sourced by a combinatorial pin. This is not
 good design practice. Use the CE pin to control the loading of data into the
 flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net segment2/counter_10_and0000
 is sourced by a combinatorial pin. This is not good design practice. Use the
 CE pin to control the loading of data into the flip-flop.
WARNING:Route:455 - CLK Net:segment2/ret may have excessive skew because 
WARNING:Route:455 - CLK Net:segment2/counter_1_cmp_eq0000 may have excessive skew because 
WARNING:Route:455 - CLK Net:segment2/counter_10_and0000 may have excessive skew because 
WARNING:PhysDesignRules:372 - Gated clock. Clock net
 segment2/counter_1_cmp_eq0000 is sourced by a combinatorial pin. This is not
 good design practice. Use the CE pin to control the loading of data into the
 flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net segment2/counter_10_and0000
 is sourced by a combinatorial pin. This is not good design practice. Use the
 CE pin to control the loading of data into the flip-flop.

And my code looks like this https://www.dropbox.com/s/9lytyrdn9f4mh1b/randomnumber_medGame.rar

I would be very grate if someone could point out what the problem is.

A huge problem is when test changes value in one module, the other module shall react on it, but the segment doesn't show the right combination which irretates me alot.

Answer 1

One of your major problems is in test.vhd. You have no declaration at all for you entity. There are no inputs to that block, nor outputs. test.vhd is all on its own. It is bad practice to not have an entity declaration. I am surprised that it even synthesized.

What it looks like you are trying to do in test is to create a new clock. If that is what you are doing, you are going about it wrong. The best practice for splitting a clock is to use a register and a counter. When the counter reaches its max, have it change an intermediate signal, something not called clock. Maybe name it half_clock or my_clock.

signal my_clock : std_logic := 0;
signal counter, counter_next : natural := 0; --use a type where addition is easy
process(clk)
begin
if(clk'event = '1') then --clk is the board clk. My FPGA runs it a 50 MHZ
 counter <= counter_next;
 counter_next <= counter_next +1;
 if(counter = MAX) then --insert your max counter number into MAX
 counter <= '0';
 --toggle your my_clock signal here
 end if;
end if;
end process;

This sudo code should save you from your gate clock warning.

As for the gated latches, make sure you have covered every case possible. Remember that with std_logic there are 9 different possibilities. Always have an else case that covers the un-enumerated cases. The keyword 'others' is very useful in this case.

Also, what set of tools are you using and what board?

• Simon Richter: Wouldn't you need to assign to counter_next?
• Carlton Banks: xilinx ISE and Spartan Nexys FGPA board. I am quite unsure which warning you are referring to..
• Carlton Banks: well.. my prescaler is exactly made like that.. So...